Time-to-digital converter (TDC) is one of the important blocks in most of the digital systems that need to have high resolution. Time difference amplifier (TDA) is used in TDC for increasing the resolution. In this study, an all-digital TDA is proposed. The proposed TDA uses the delay lines with difference delay for amplifying. The proposed circuit is designed and simulated in 65 nm CMOS technology and has a gain of ten and a chip area of about 0.003 mm². The calculated maximum gain error is 5%. The proposed TDA consumes 0.94 mW power under 1.1 V supply voltage.

Silicon fin field-effect transistor (FinFET) devices with gate–source/drain underlap fin length (L _un) structures have been used for effective reduction in short channel effects (SCEs) from many years. Here, investigations have been performed on the FinFET structure with In_0.53Ga_0.47As material. Three-dimensional technology computer-aided design simulations for 14 nm channel length In_0.53Ga_0.47As FinFETs with underlap have been conducted by incorporating various effects to analyse the influence of interface traps on the device. The dominance of traps is investigated on SCE and intrinsic delay to assess the trend on underlap devices. The impact on threshold voltage and on current due to metal gate work function (MGWF) variation has been also demonstrated. Simulations have been carried out for L _un = 0, 3, 6, and 9 nm with interface trap density of 10¹² and 10¹⁴ cm^–2 eV^–1. Improvement in the subthreshold swing (SS) is observed as the L _un increases but at the cost of intrinsic delay. However, the improvement in SS after L _un = 6 nm is nearly constant. It has been also observed that the relative standard deviation of the threshold voltage and on current variation due to MGWF variation improves as the L _un increases till 6 nm after that this improvement is not very significant.

In this work, the authors investigate analogue and radio-frequency (RF) figures-of-merit (FOM) of electrostatically-doped ferroelectric Schottky-barrier tunnel field-effect transistor (FET) (ED-FE-SBTFET) by deploying PZT (lead zirconium titanate) gate stack and dopant-free technology. This PZT gate stack results in negative capacitance behaviour as a result of the positive feedback among the electric dipoles within it. It realises an intrinsic amplifier to amplify the surface potential due to the applied gate bias and enhances the gate controllability significantly. As a result it facilitates lower ambipolar current, considerably high drive current and faster switching transitions. As the structure is realised by using dopant-free technique it ensures simplified fabrication process as it avoids the need of ion implantation and thermal annealing, reduces thermal budget. Here, a detailed comparison is carried-out between charge plasma Schottky-barrier tunnel FET and ED-FE-TFET for their high frequency FOMs such as cut-off frequency (), gain bandwidth product, transconductance generation factor and so on. The higher ratio of ED-FE-SBTFET reduces the static and dynamic both types of powers in digital circuits, while higher ratio ensures lower bias power of an amplifier.

Reversible logic is an emerging digital design paradigm which promises low energy dissipation; thanks to its information-lossless nature. True potential of this exciting concept can only be assessed by facing the design of practical complexity applications. Low density parity check (LDPC) decoding is one such application from forward error correction domain. The core of LDPC decoding is the check node (CN) processor, which executes the decoding algorithm and constitutes a major portion of decoder's overall power consumption. This work proposes a low-power LDPC CN architecture using reversible logic gates. Transistor level design and full custom layout of proposed architecture is carried out on UMC complementary metal–oxide–semiconductor technology. All reversible blocks of proposed CN are optimised for quantum cost, garbage outputs and transistor count. The CN functionality is validated with post-layout simulations, layout versus schematic checks and design rule checks. The proposed CN occupies a post-layout area of 0.013 mm², achieves up to 4.3 GHz frequency and consumes power. The performance of proposed CN is also compared with its implementation using irreversible gates. The proposed CN achieves about 300% reduction in power delay product with affordable complexity as compared to its classical implementation.

In this study, a drain current model of bilayer graphene field-effect transistor (GFET) has been developed. The Boltzmann transport approach is considered to develop this model including the scattering effects. The effects of optical phonon scattering, acoustic phonon scattering and carrier-carrier scattering have been included. The effective voltages at top and back gates induce net mobile sheet charge density in graphene channel. Mobile sheet charge density helps to determine the quantum capacitance. Channel potential is derived from equivalent circuit. The electronic transport phenomena of carriers in channel are explained for the contribution of both electron and hole charge density. Finally, the expression of drain current is determined using the Boltzmann transport equation under non-equilibrium condition. Contact resistances at source and drain regions are considered to determine the accurate drain current. The small signal parameters of GFET are determined from drain current and net charge density, and finally using these parameters the authors have calculated the cut-off frequency of the model. We validate the model with several contemporary experimental results. Utilising the model, we have also explored the impact of back-gate bias, top-gate bias and channel length on the device characteristics.

In recent years, ultra-low-voltage (ULV) operation is gaining more importance for achieving minimum energy consumption. Full adder is the basic computational arithmetic block in many of the computing and signal/image processing applications. Here, a new hybrid 1-bit full adder circuit which employs both Gate Diffusion Input (GDI) logic and multi-threshold voltage (MVT) transistor logic is reported. The main objective of the proposed MVT-GDI-based hybrid full adder design is to provide minimum energy consumption with less area. The proposed hybrid design is simulated using standard 45 nm CMOS process technology at an ULV of 0.2 V. The post-layout simulation results have shown that the proposed design achieved significant improvements in comparison with the other reported designs by achieving >57%, 92% savings in the Energy and EDP, respectively, with only 14 transistors. Monte–Carlo simulations have also been performed and is found that the proposed design methodology yields full functionality and robustness against local and global process variations. Normalised energy metrics to 32 and 22 nm technologies shows that the proposed design achieves >57% energy savings in prior to the recent works.

Here, the authors present a model order reduction (MOR) framework based on singular perturbation approximation to accelerate the simulation of high-fidelity power electronic converters. The problem of slow simulation speeds caused due to the wide span of the eigenvalues is mitigated by implementing the proposed framework. The dynamics of the original stiff system is approximated by neglecting the transient contribution of the non-dominant eigenvalues and retaining the steady-state contribution of all the eigenvalues of the system. The model reduction problem has been reformulated to fit the switched nature of these circuits. An error bound for the approximation method has been derived. The method is demonstrated on a DC–DC boost converter and a Class-E amplifier. Significant improvement in speed and reduction in the size of the solution arrays is achieved. It is seen that the reduced-order models are able to replicate the response of the original models and the approximation error is within acceptable limits.

This study proposes two new emulator circuits of floating (grounded) flux-controlled incremental/decremental memristor, based on modified z-copy current–voltage differencing transconductance amplifier (VDTA). The circuits use only one VDTA as an active element, a single grounded capacitor and a variable number of grounded resistors, which benefit from the integrated circuit. Furthermore, it can utilise metal–oxide–semiconductor (MOS) capacitance instead of the external capacitor in the circuit. It does not consist of any multiplication circuit block to obtain non-linear behaviour of the memristor. The parameters of the proposed memristor emulator can be tuned electronically by changing the biasing current of the VDTA. Change of the transconductance gain of the VDTA provides an advantage in the form of the externally controllable memristor. Through the simulation program with integrated circuit emphasis (SPICE) simulation which was carried out on the basis of 0.18 μm complementary MOS technology and experimental results using two MAX435 commercial devices as an active element, all theoretical assumptions and conclusions were reached in different operating frequencies, the capacitance value and process corner. The simulation test results have shown that the maximum frequency is 50 MHz.

In this study, an effective and efficient approach for reliability analysis is developed to bridge the gap between device-level reliability and that at the product level. Continual reduction of device dimensions, gate-oxide and increase in channel doping results in an increased electric field which is introducing most of the reliability concerns. Four most important reliability issues impacting circuit design are hot carrier injection, bias temperature instability, time-dependent dielectric breakdown and self-heating. As the second-generation current controlled conveyor (CCCII) circuit are used to implement oscillator, filter clock and so on, which are working continuously even in sleep mode. So it is important to take care of all the reliability aspects while designing CCCII. There is a challenge in complex design to identify which devices (MOS, resistor and capacitor) are susceptible to degradation and then redesign and mitigate this effect for a robust and reliable design. The objective of this work is to detect reliability issues and design a programmable current conveyor which can work safely for a long duration. The circuit has been designed and simulated using 28 nm CMOS technology model parameters on Cadence Virtuoso/AMS environment (ELDO simulator) using ± 1.8 V supply voltage and results have been verified with post-layout netlist.

Wireless telemetry has recently become a very important feature for healthcare monitoring and wearable systems. Several factors such as reliability, power budget, and cost impose design constraints for data transmission. Literature reported transmitters characterised by lower energy efficiency for low data rate operations and are not quite suitable for low-power biomedical applications. To overcome these constraints, this paper presents an impulse radio ultra-wideband (IR-UWB) transmitter that implements a heavy duty-cycling approach to achieve low power consumption. The transmitter is designed to be used for a non-invasive wireless respiration monitoring and apnoea detection system for premature infants. The transmitter is designed and fabricated in 130 nm standard CMOS process achieving 9.12 µW of power consumption and 91.2 pJ per pulse at 100 kbps data rate.

Home-based health care applications are rapidly gaining popularity, enabling a renewed focus on the design of low-power and low-noise front-end circuitry. In this context, the evaluation of low-frequency biomedical signals, such as the respiration pattern, benefits from the design of a front-end amplifier with reduced power consumption and low noise. Continuous efforts on improving the performances of respiration-monitoring devices have resulted in the reduction of noise and motion artefacts by increasing complexity (e.g. complex algorithms or high precision filtering) at the expense of increased power consumption. This study is focused on the design of a fully integrated charge amplifier for respiration monitoring based on a pyroelectric sensor. Simulation and test results show a power consumption of 1.8 µW, an active die area of 0.085 mm², a bandwidth in the range from 10 mHz to 13 kHz, and a remarkable noise efficiency factor of ∼2.79, which fits well with the development of an energy efficient wearable device.

Analogue Quaternary logic is very promising logic for multi-valued logic implementation. Four states can be generated in different ways. This paper shows the generation of four states in two different semiconductor MOSFETs by modifying their gate structure as well as channel structure. In three well-spatial wave-function switched FET (SWSFET), the four states are generated by connecting their drain terminals. On the other hand, in the quantum dot gate–spatial wave-function switched FET (QDG-SWSFET), the four states are generated by the combining effects of SWSFET and QDGFET.

Using well-calibrated device simulation, the analogue performance of 20 nm double-gate junctionless transistors (JLTs) is investigated in terms of transconductance (g _m), output conductance (g _d) for various underlap spacer asymmetricity and dielectric constant (k) values. The spacer length is varied ranging 1–6 nm on both source (L _S) and drain sides (L _D) while keeping their sum fixed at 12 nm. Obtained results show that for both n- and p-metal-oxide-semiconductor field-effect transistors (FETs), a longer LD increases gm exhibiting weak sensitivity to variations in k while gd increases and decreases with higher and lower k. The present findings reveal that the highest voltage gain of 46.3 and largest gain bandwidth (GBW) of 676 GHz are obtained for complementary metal–oxide–semiconductor (CMOS) amplifiers featuring both n and p transistors with L _S = 11 nm, L _D = 1 nm and k = 80 and L _S = 1 nm, L _D = 11 nm and k = 3.9; both figures are quite higher compared with their symmetric counterpart. The studies manifest that such an asymmetric dielectric spacer engineering could be employed in designing high performance nanoscale CMOS amplifiers without increasing hardly any process complexity and cost while providing augmented GBW compared with reported amplifiers based on molybdenum disulphide transistors and tunnel FETs.

Here, an analytical modelling of drain current is presented for double gate-all-around (DGAA) MOSFETs. A common feature in all the multi-gate (MG) MOSFETs is that the channel charge in the sub-threshold regime is proportional to the channel cross-sectional area; whereas, the inversion charges above threshold locate near the Si/SiO₂ interfaces and are proportional to the total gated perimeter of the channel body. This distinctive feature introduces the notion of equivalent charge and has been widely used to model the drain current of any arbitrary non-classical MOSFET architecture. The authors have extended the aforementioned quasi-approach to model the drain current of DGAA MOSFET. The total gated perimeter of DGAA MOSFET is mapped by the gated perimeter of two GAA MOSFETs with different radii for the calculation of surface inversion charges above threshold. The currents obtained from two GAA MOSFETs are summed up to obtain the current of DGAA MOSFET. I–V characteristics and transconductance of the device for various physical parameters are compared and analysed with the numerical simulation results obtained from Visual-TCAD of Cogenda Int.

Sub-threshold voltage operated circuits are the future for ultra-low-power applications. These circuits are inherently slow due to the very small sub-threshold currents. Here, the authors propose two approaches for improving the speed of SWCNT bundle interconnects driven by CNTFET-based circuits under sub-threshold conditions. First, the authors modulate the channel length of the CNTFETs that are used in the driver circuits to increase sub-threshold output current. The output current is maximum when the channel length is optimised to 15 nm. Second, the authors design driver circuits made of CNTFET-based inverters and transmission gates for SWCNT bundle interconnects at sub-threshold voltages. The authors consider five different configurations of the driver and load circuits. SPICE simulations show that transmission gates play a vital role in driver circuits by reducing the propagation delay and increasing the switching speed at high frequencies. Finally, the authors perform temperature-dependent analysis of the best cases from the proposed circuits and show that the propagation delay and power dissipated by them increases drastically at increased temperatures up to 500 K.

Quantum dot cellular automata (QCA) is a hopeful technology in the field of nanotechnology that seems to suite well with signal-processing needs. It is concerned with great interest because of its benefits such as ultra-low power consumption, small size and can operate at one Terahertz. The multiply accumulator (MAC) unit is considered as one of the essential operations in digital signal processing (DSP). In the real-time DSP systems, several applications like speech processing, video coding, and digital filtering etc. require MAC operations. However, the power dissipation and area are the most significant aspects in these systems. Here, the authors design low power MAC unit based on QCA technology. QCADesigner version 2.0.3 is used to validate the accuracy of the proposed circuit. The reliability of this unit is taken at different temperatures. The power dissipation is estimated using QCAPro tool. The total power consumed by this unit is 2.183 μW. The proposed circuit has 90% improvement in terms of power over complementary metal–oxide–semiconductor (CMOS) circuits. Since the works in the field of QCA logic signal processing has started to progress, the suggested contribution will give rise to a new thread of research in the field of real-time signal and image treatment.

To overcome the short channel effects of a regular field effect diode (FED), this paper proposes a novel nanoscale FED. The novel FED has a simple structure that can be fabricated by the standard CMOS process technology. Both regular and novel FEDs are simulated using TCAD tools as a semiconductor drift-diffusion solver. Simulation results show that the novel device can operate properly at nanoscale channel length. The I _ON/I _OFF ratio of the novel FED is several orders of magnitude higher than of the regular FED.

A power- and variability-aware non-volatile resistive random access memory (RRAM) cell is presented. Non-volatility is achieved due to the use of a memristor as a memory element, which when integrated with a carbon nanotube field-effect transistor (CNFET) helps achieve tremendous robustness against process variation. The half-select issue, inherent in the 2T2M RRAM cell (state-of-the-art design based on the memristor) have been resolved and its circuit parameters have been compared with those of the proposed cell. Also, the proposed cell has been compared with the standard 6T SRAM (S6T) cell. The proposed cell shows 1.6×/4.08× narrower read delay/write delay variability compared with 2T2M. 5CNFET2M also shows 1.8× narrower read delay variability than that of S6T. Furthermore, the proposed cell shows 6.9× shorter write delay in comparison with the 2T2M RRAM cell. 5CNFET2M consumes 10⁶×/1.34× lower power during hold mode compared with the conventional 6T static random access memory/2T2M RRAM cell. Furthermore, the proposed cell also shows improvement in hold power variability compared with both the cells. All the simulated data, presented here are at the nominal supply voltage of 1 V. These improvements are gained at the expense of slightly longer read time compared with 2T2M/S6T and 31.3× longer write delay compared with S6T.

Robust Chaos occurring in piecewise smooth dynamical systems is very important in practical applications. It is defined by the absence of periodic windows and coexisting attractors in some neighbourhood of the parameter space. In earlier works, the occurrence of robust chaos was reported in the context of piecewise linear 1D and 2D maps, and regions of occurrences have been investigated in 1D and 2D switching circuits. Here, it has been reported the first experimental observation of this phenomenon in a 3D electronic switching system and obtain the region of parameter space by constructing a discrete map of the system.

This paper designs an engineering realisation of Doppler parameters estimation circuit for synthetic aperture radar (SAR) imaging system based on motion compensation. The algorithms for Doppler centroid frequency and Doppler frequency rate estimations are selected in advance. By optimising the mapping process from algorithm to hardware circuit and selecting proper floating-point data bit width, logical resources can be reduced significantly. Verified with an FPGA-based PCB platform, the proposed design works properly and with controllable computing error.