In this study, the authors demonstrate the potentiality of the integration of low-density parity-check codes with a full self-seeded optical architecture using advanced optical and electrical models. This study aims to show the performances that one can expect from this association in the context of cloud radio access network (C-RAN). Different decoding algorithms have been studied over additive white Gaussian noise channel. Hard-decision algorithm of Gradient descent bit flipping (GDBF) is finally chosen since it represents the best trade-off between the complexity of decoder and the performance. Furthermore, the authors show that a small 2-bit quantification is sufficient, which can increase the data rate and decrease the latency of decoder in comparison with a more complex ADs. The same performance of floating point GDBF is achieved by using the new algorithm Balanced Weighted GDBF (BWGDBF) with 2-bit quantification. Finally, the authors have succeeded to implement BWGDBF algorithm on the FPGA Spartan 6 xc6slx16. The proposed system exhibits very good performances since it is able to achieve 2.5 Gb/s throughput in the C-RAN context.

This study presents a survey on the existing fault diagnosis methods (FDMs) of the switch devices for the rapidly developing modular multilevel converters (MMCs). Three categories, namely mechanism-based, signal processing-based and artificial intelligence-based FDMs, are evaluated and summarised depending on the operating principles. Mechanism-based FDMs detect the faults by comparing the inner characteristics of MMC or their derived parameters with the expected values. Signal processing-based FDMs detect the faults via comparing the processed output voltage or current with their expected values. Artificial intelligence-based FDMs detect the faults in the way of employing a trained intelligent classifier. Methods belonging to each category are introduced in detail via comparing a lot of criteria of the FDMs. Then, a figure-of-merit is defined to evaluate various FDMs. Finally, the summary is given and the developing tendency is recommended for future work.

This study introduces the generalised canonical transfer function (TF) of the band-pass negative group delay (NGD) circuit. The principle to identify the unfamiliar band-pass NGD circuits is suggested. Similar to the filter theory, the band-pass NGD TF can be established from low-pass to band-pass frequency transform. The fundamental characteristics of the NGD topology are described. The canonical TF feasibility is concretised with the second-order equivalent impedance constituted by passive elements. The synthesis formulas in function of the desired NGD level and bandwidth are analytically established. Application examples of band-pass NGD impedance synthesis, designed and fabricated are proposed as a proof of concept. Prototypes of band-pass NGD circuits with centre frequencies 1 and 1.5 MHz for the targeted group delay optimal values, respectively, −1 and −1.5 µs are designed and fabricated. As expected, band-pass NGD results in good agreement with the theoretical prediction were obtained with simple lumped circuits. In the future, thanks to theory simplicity, the NGD band-pass cell can be potentially useful for the signal delay correction.

Flexible, multiple-clock-cycle, hardware design for the quasi-maximum likelihood (QML) algorithm core realisation for the polynomial phase signals (PPSs) estimation is proposed. The QML algorithm significantly outperforms existing PPS estimators in terms of accuracy. However, its practical applications require efficient software and hardware systems. The main challenges in the proposed hardware development with respect to existing systems for time–frequency (TF) analysis are realisation of TF representation based instantaneous frequency estimator, the polynomial regression, and phase extraction. The developed design is tested on a PPS corrupted by a white Gaussian noise and verified by a field programmable gate array circuit design. All implementation and verification details are provided along with the comparison of the results achieved by hardware and software implementations.

A simple vertical organic field-effect transistor (VOFET) structure has been fabricated using ambipolar 6, 13-bis (triisopropylsilyl ethynyl) pentacene (TIPSP) with a channel length (L) of 90 nm. This device can operate at –2 V which is much lower than the voltage, reported so far for the organic devices based on TIPSP. The first time, the authors are using transistor efficiency to extract VOFET's parameters. The threshold voltage (V _th) of the device has been found to vary between 0.18 and 0.38 V with the current on/off ratio (I _on /I _off) of 10⁴. The mobility (µ) of the device has been calculated as 0.62 cm²/Vs. The sub-threshold slope, transconductance (g_m ), output conductance (g _d), and early voltage (V _E) have been found to be 140 ± 30 mV/decade, 2 µS, 10⁻⁶ S, and 1.3 ± 2 V, respectively.

In this study, a boundary analysis is carried out for the derivative of driving point impedance (DPI) functions, which is mainly used for the synthesis of networks containing resistor-inductor, resistor–capacitor and resistor–inductor–capacitor circuits. It is known that DPI function, , is an analytic function defined on the right half of the s-plane. In this study, the authors present four theorems using the modulus of the derivative of DPI function, , by assuming the function is also analytic at the boundary point on the imaginary axis and finally, the sharpness of the inequalities obtained in the presented theorems are proved. It is also shown that simple inductor–capacitor tank circuits and higher-order filters are synthesised using the unique DPI functions obtained in each theorem.

Analogue signal processing (ASP) is a promising alternative to digital signal processing techniques in future telecommunication and data-processing solutions. Second-order all-pass delay networks – the building blocks of ASPs – are currently primarily implemented in off-chip planar media, which is unsuited for volume production. In this study, a novel on-chip complementary metal–oxide–semiconductor (CMOS) second-order all-pass network is proposed that includes a post-production tuning mechanism. It is shown that automated tuning with a genetic local optimiser can compensate for CMOS process variation and parasitics, which make physical realisation otherwise infeasible. Measurements indicate a post-tuning bandwidth of 280 MHz, peak-to-nominal delay variation of 10 ns and magnitude variation of 3.1 dB. This is the first time that measurement results have been reported for an active inductorless on-chip second-order all-pass network with a delay Q-value larger than 1.

A carbon nanotube field effect transistor (CNTFET) emerged as an alternative to the complementary metal oxide semiconductor (CMOS) for implementing low-power high-speed very-large-scale integration circuits. In this study, the CNTFET technology is discussed that has faster switching speed and high-carrier mobility as compared with the CMOS technology. A new technique ultra-low power dynamic node driven transistor domino logic is proposed for designing low-power domino logic circuits. 2, 4, 8 and 16 input logic gates are simulated using the proposed and existing techniques. Simulation is done on an H-Spice Stanford CNFET 32 nm model at a clock frequency of 200 MHz using the CNTFET technology. The proposed technique shows a maximum power reduction of 57.14% and a maximum delay reduction of 50.24% as compared with the current mirror footed domino logic technique in CNTFET technology. The proposed technique has a maximum power reduction of 96.61% in the CNTFET technology as compared with its counterpart in the CMOS technology for the two-input OR gate. The proposed technique shows a maximum improvement of 1.39× in unity noise gain as compared with the conditional stacked keeper domino logic technique for 16 input OR gates in the CNTFET technology at 200 MHz.

Two new analytical synthesis methods are proposed for synthesising an nth odd-order elliptic high-pass (HP) filter using operational trans-resistance amplifiers (OTRAs). The analytical synthesis scheme is based on the assumption of infinite trans-resistance R _m for the OTRA. The H-spice simulations of the realised elliptic third-order HP filters show that the realisation using less number of OTRAs has a performance better than that which uses more number of OTRAs, as is to be expected in view of the assumption that R _m is infinite, when in fact it is finite in practice. However, it is shown that by slightly adjusting a single resistor, the amplitude–frequency response can be made close to the theoretical response.

This study suggests a proportional-type output-voltage control algorithm of a three-phase inverter for uninterruptible power supply applications with performance-recovery and offset-free properties. It makes the two contributions. The first one is to introduce first-order disturbance observers (DOBs) so as to exponentially estimate disturbances originating from model-plant mismatches. The second one is to rigorously prove that the proposed proportional-type feedback-linearising controller equipped with DOBs guarantees performance-recovery and offset-free properties. The experimental results conducted in this study, which uses a 10 kW three-phase inverter with an output capacitor, confirm that the closed-loop performance is satisfactory in both transient and steady-state periods.

Here, the authors propose a new family of ternary circuits for a general design perspective. Besides presenting an efficient ternary logical circuit approaches, the focus of this study is also about introducing techniques for reducing the performance metric cost of the proposed family. Basic ternary arithmetic gates, ternary half-adder, and ternary partial product generator are also proposed for two different levels. First, direct transistor level implementation is considered, next a modification in the gate level implementation representing a state-of-the-art approach is addressed. Carbon nanotube FET (CNFET) is considered as an appropriate technology for implementation and realisation of ternary circuits. Therefore, simulations are carried out at 32 nm CNFET model using Synopsis HSpice tool. Simulation results show the advantages of ternary structures considering the proposed method.

A joint background calibration scheme is proposed for the gain and timing mismatch errors in time-interleaved analogue-to-digital converts (TI ADCs). Mixed-signal calibration is adopted for timing mismatch without using correlators or multi-tap digital filters, while the gain mismatch is estimated and calibrated all digitally based on the moving average of the derivative for each channel's output. Therefore, the influence of offset mismatch on the estimation accuracy of the gain error can be eliminated completely. To reduce hardware cost as much as possible, most of the arithmetic blocks are reused for gain and timing mismatch estimation. Behavioural simulation with a 12 bit, 2 GSPS two-channel TI ADC and measurement results from a commercial 12 bit 3.6 GSPS two-channel TI ADC show that the proposed joint calibration scheme can effectively correct the gain and timing mismatch errors.

This study presents the design and experimental characterisation of single-layer solenoid air-core inductors. The analytical expressions for the winding inductance, self-capacitance, and winding resistance are derived. The inductor properties are analysed up to the first self-resonant frequency. The procedure to design air-core inductors for high-frequency (HF) applications is provided. Experimental validations of the analytical equations are given. A single-layer air-core inductor was designed, built, and measured. The bandwidth of the designed inductor obtained from theoretical predictions was about 100 MHz. The measured quality factor was 181 at 1 MHz. The results of this study are useful for engineers and designers in the areas of power supplies, datacentres, radio-frequency power amplifiers, radio-frequency transmitters, and HF filters.

Here, a fast digital foreground calibration technique to calibrate the gain error in the pipelined analogue-to-digital converter (ADC) is proposed. The technique suggested uses maximum reference value of the ADC along with least mean squares adaptive algorithm to compensate the gain error. It avoids the use of slow but accurate reference ADC, thus saving area, power, and design efforts. The proposed calibration algorithm is implemented in Xilinx Artix-7 FPGA kit to show the effectiveness of the algorithm. After calibration, differential non-linearity improves by 30% and integral non-linearity reduces from values +60/−60 LSB to +0.77/–0.77 LSB. Also, signal to noise and distortion ratio and spurious-free dynamic range improve significantly from 35.9193 and 36.7348 to 75.3619 and 82.2884 dB, respectively, after calibration.

To reduce the excessive power consumption and eliminate the battery voltage imbalance caused in conventional method, a novel broken line detection scheme for Li-ion battery protection integrated circuits (ICs) is presented in this study. The main part of the proposed circuit consists of pull-up, pull-down current source, source-driven MOS, a control switch and a bias current source. A narrow pulse control signal is adopted to trigger broken line detection periodically so as to suppress the detection current consumption, while the disadvantage of battery voltage imbalance is overcome. The proposed circuit has been implemented in a seven cells Li-ion battery protection IC with 0.18 µm 45 V bipolar-CMOS-DMOS process successfully. The experimental results confirm that the chip can reliably detect the disconnections of Li-ion batteries and take protective measures in a wide cell voltage range from 2.2 to 4.2 V. Furthermore, based on the derivation in this study, the proposed technique can significantly reduce the detection current consumption of each cell, which is well beneficial for low power consumption and battery voltage balance.

In this study, a 4.4 MHz wireless power transfer (WPT) system was designed and implemented using a class-AB Armstrong oscillator that uses a packaged GaN on Si high electron mobility transistor. The oscillator is designed and simulated in advanced design system and then integrated with a magnetically coupled resonant WPT system. The transmitting planar coil of the WPT contains both the main and the feedback coils of the Armstrong oscillator. The whole system was implemented in a printed circuit board and tested. The DC-to-AC conversion efficiency of the simulated Armstrong oscillator is 69%. The maximum measured power transfer efficiency is 40.3% at a 2 cm distance between the transmitting and receiving coils. The input DC power of 37.5 mW provides 15.1 mW of AC power to the load with low distortion, making it suitable for low electromagnetic interference, size, power and cost applications such as biomedical implants.

This study presents a fourth-order, low-pass Butterworth transconductor–capacitor filter with tunable bandwidth for biomedical signal processing front-ends. An architecture has been proposed for realising very low transconductance values with tunability. This transconductor architecture makes it possible to realise a fully differential filter without the need for explicit common-mode feedback circuit. The filter has two tuning schemes, a resistor-based tuning (R-tuning) and a switched transconductor-based tuning (D-tuning). With R-tuning, the bandwidth is adjustable between 1 and 70 Hz and with D-tuning, the tuning range is 30 mHz–100 Hz. The filter has been designed in united microelectronics corporation (UMC) 0.18 µm complementary metal–oxide–semiconductor process. In terms of figure-of-merit, the proposed filter is found to be on par with the filters reported in the literature.

Lithium-ion battery as an efficient, sustainable, and clean energy for electric vehicles (EVs) and smart devices becomes more popular with the worldwide demand for reduction of greenhouse gas emission. In all kinds of applications, an accurate real-time estimation for state of charge (SOC) of battery is necessary. Some conventional methods usually need to sample both battery currents and voltages. This article presents a novel SOC estimation algorithm without current detection. This algorithm just acquires the port voltages of cell to calculate the open-circuit voltage (OCV) which is related to SOC. By extracting a large number of battery voltages based on a step response, some important parameters that can track battery working process are determined. In order to verify the algorithm feasibility and accuracy, it has been tested on a commercial common field-programmable gate array (FPGA) in different application conditions. The algorithm accuracy is mainly limited by model accuracy and sampling sensor accuracy. The maximum error between ideal SOC and calculated SOC by this algorithm is within 4%, and the mean error is about 0.99%. So, this high-feasibility, accredited accuracy, easy integration, and low-cost solution has bright potential in smarter future.

This study presents a very-large-scale integration (VLSI) architecture for the triangular windowed sliding discrete Fourier transform (SDFT) based on COordinate rotation DIgital computer (CORDIC) algorithm. In the literature, the triangular windowed SDFT is obtained by direct cascading of two SDFT modules, whereas the idea of direct cascading leads to the error in the odd bins of the spectrum. The proposed architecture is modified to provide the correct outputs with a high-throughput rate compared to the existing designs. The SDFT has a recursive structure, and therefore it accumulates the error over iterations as the computation proceeds. A refreshing mechanism is utilised to limit the inaccuracy at the final output. The concept of generalised architecture as an area efficient implementation for obtaining more number of discrete Fourier transform (DFT) bins is introduced. An architecture is implemented using Verilog HDL on FPGA as well as in ASIC platform, and its arithmetic verification is performed in MATLAB.

This study presents an architecture and study of closed-loop continuous time delta-sigma modulation utilising only voltage-controlled oscillators (VCOs) and digital elements. It incorporates a VCO-based integrator in which the offset due to the carrier frequency is digitally subtracted. Unlike some prior structures, an extra VCO for reference signal generation is not necessary which can lead to a reduction in power consumption, area and noise. In addition, in comparison to a recently reported structure, the VCO is placed inside the feedback loop, so the input signal swing of the VCO is decreased and the linearity is improved. However, the proposed structure suffers from two noise folding effects at low frequencies which degrade the dynamic range of the modulator. These two noise folding effects will be analysed and it will be shown that these problems can be tackled by the right choice of and appropriate design. Behavioural simulations are done for the proposed structure to confirm the structure's performance.