The solutions of inverter switch and routing scheme are integrated to develop a mobile controlled energy saving system (MCESS). For the transient response problem of an n-channel metal-oxide-semiconductor field-effect transistor acting as an invert switch, and a routing scheme is solved for developing the MCESS. It can be claimed that all the mentioned previously schemes are very challenge for addressing the problems in the design of an analogue processing circuit and the implementation of Android applications (or Apps). The developed MCESS is experimentally verified automatically switch for adjusting the energy output appropriately. A control system with a solution of MCESS can replace the traditional sustainable energy systems, and obtain much longer lifetime and a steady state of the storage equipment. Furthermore, the proposed MCESS integrates Apps developed on a smart device using the Android platform with different wireless protocols, such as WiFi, Bluetooth for controlling the system with contactless. Moreover, there much experience in the development of MCESS is provided audiences with useful materials, for example a routing solution that employs wireless local area network with the WiFi protocol is implemented to transmit packets of the regulator circuit and the instant feedback display.

A novel optically triggered global shutter image sensor using single photon avalanche diodes (SPAD) is proposed. An optical signal with a switching frequency of 100 MHz illuminates SPADs and acts as both a shutter and reset signal source by means of free space optics. Each image sensor pixel contains a front side illuminated SPAD, while a pinned photodiode is used to collect the scene's light from the chip back side to increase the pixel fill factor. The pixel is designed and post layout simulated in 90 nm complementary metal oxide semiconductor technology. Moreover, the jitter performance of 76.2 ps (excluding SPAD and light source jitter) is achieved. The image sensor pixel pitch is 90 µm with 2.27 mW power consumption per pixel with a fill factor of above 90%. The image sensor pixel can take 64 different frames at the rate of 50 Mfps and store until the global readout phase.

An efficient numerical model of silicon-on-insulator (SOI) four-gate transistors (G⁴FET) and its implementation in circuit simulator is presented here. A set of available data for different operating conditions is used to empirically determine the parameters of this model and a different set of test data is used to verify its predictive accuracy. This DC model is used to express the drain current as a single multivariate regression polynomial with its validity spanning across different possible operating regions as long as the chosen independent variables lie within the range of data set used to develop the model. The continuity of the polynomial model and its derivatives makes it particularly suitable for implementation in a circuit simulator. Models for both n-channel and p-channel G⁴FETs have been developed and validated using TCAD and experimental data and are successfully implemented in SPICE simulator for simulating two experimentally demonstrated G⁴FET circuits.

In recent years, there is a trend towards the development of reconfigurable circuits where devices using them offer flexibility and performance. Different technologies are explored, such as threshold logic gates (TLGs), which are one of the most promising future technologies, and researchers are examining and improving different characteristics such as density, performance and power dissipation. This research presents a 4-bit arithmetic logic unit (ALU), which was designed using TLGs through reconfigurable logic blocks with a universal circuit configured with three stages based on a floating-gate metal oxide semiconductor transistor with more than one control gate, which was named neu-complementary metal oxide semiconductor (ν-CMOS). The main contribution is that this device is configured as a ν-CMOS inverter and has the ability to program the threshold voltage of its transfer curve by applying an external voltage to the additional control gates. The number of input bits and the magnitude of the weighted input capacitances related to control gates of the ν-CMOS inverters is obtained and analyzed by using the graphical method (floating-gate potential diagram). Finally, the proposed 4-bit ALU shows similar results as those measured from the ALUs implemented in the field programmable gate array evaluation kit and the Motorola chip MC14581B.

The Burrows–Wheeler transformation (BWT) is a reversible block sorting transform that is an integral part of many data compression algorithms. This work proposes a memory-efficient pipelined decoder for the BWT. In particular, the authors consider the limited context order BWT that has low memory requirements and enable fast encoding. However, the decoding of the limited context order BWT is typically much slower than the encoding. The proposed decoder pipeline provides a fast inverse BWT by splitting the decoding into several processing stages which are executed in parallel.

This study presents an implantable passive wireless blood pressure sensor using an inductive coupling wireless sensing technique that is designed for long-term monitoring of blood pressure in hypertension patients. This sensor includes a gold tapered square spiral inductor and a circular capacitor with a polyimide diaphragm. The purpose of this study is to minimise the dimension of the sensor due to the limitation of space around the vessel; therefore, a microelectromechanical systems (MEMS) inductor and a capacitor with small dimension and high sensitivity are used. In this structure, the diaphragm is deflected by applied pressure which capacitance and then resonance frequency are changed. These changes are sensed remotely with inductive coupling, which eliminates the need of wires connection for monitoring. In this method, a blood pressure signal can be obtained by measuring the impedance phase dip from the external coil. The distance between two coils is 8 mm. The sensor is designed to provide a resonance frequency range of 282–381 MHz for a pressure range of 0–250 mmHg. Simulation has been done using COMSOL Multiphysics and ADS software. The dimension of the sensor is 2.2 mm × 2.2 mm and the sensitivity of the sensor is 1550. This sensor has a small size and high sensitivity rather than previous works.

For the first time halfnium oxide (HfO₂) is being incorporated in the dual-k spacers and has been used in bulk planar junctionless transistor (BPJLT). It has been found that incorporating HfO₂ in spacers not only improves the electrostatic integrity but also improves digital/analogue circuit performance of the BPJLT. Further, the increased effective gate length due to fringing electric field through HfO₂ to thin body reduces OFF-state leakage, subthreshold swing and drain-induced barrier lowering by ∼60, ∼15 and ∼30%, respectively. Although the presence of HfO₂ inner spacer layer at source/drain increases the parasitic capacitances, the significant improvement in ON-state drive current reduces the intrinsic gate delay of the device. Further, the analogue circuit figures of merit such as transconductance, transconductance generation factor and the intrinsic gain of the proposed device are found to be significantly improved over the conventional BPJLT device. The mixed mode device/circuit simulation results of an inverter and the common source amplifier show that leakage power dissipation, propagation delay and the open-circuit voltage gain of the proposed device are improved significantly over the conventional BPJLT device. The fabrication process flow of this novel device has also been proposed.

A novel non-isolated dc–dc converter topology for high step-up applications is presented in this study. The input side of the proposed converter can be derived with the help of a zeta converter, replacing the two inductors of basic zeta by a coupled inductor with double windings. At the same time, the switched-capacitor circuits are constituted through the secondary side of coupled inductor and diode capacitors, which enhance the voltage gain without a large duty cycle. The proposed converter can isolate the dc current from the electric source when it is switched off, and the voltage stress of the active switch is restrained through a passive regenerative snubber. Both the primary and secondary leakage energies of the coupled inductor can be recycled. The inrush current problem of diode capacitors is restrained by the leakage inductance of the coupled inductor. The above characteristics are the reason for the high-voltage gain and high efficiency of the converter. The principles of operation and steady-state analyses are described in detail. A compact circuit has been implemented in the laboratory, and the experimental results confirm the analysis of the presented converter.

Fractional-order circuits find a widespread use in different engineering applications. The problem of realising fractional-order circuits has been discussed by several authors, however, it is far from being solved. Realising fractional-order resistorless passive network with three element orders is been studied. At first, this study extends the two-variable reactance matrix synthesis method to three-variable case, and then proposes a synthesis method of fractional-order reactance matrix with three element orders by variable substitution. The process in above methods mainly involves variable substitution, decomposition of three-variable reactance matrix, extraction of unit inductors, Laurent series expansion, spectral factorisation of two-variable positive semidefinite Hermitian matrix and synthesis of univariable reactance matrix. Then the above-mentioned synthesis process is illustrated by two examples.

The multiplier is one of the most important arithmetic units, which is an essential part of an IC system and affects its efficiency dramatically. The Booth structure of a multiplier is a wide-used and efficient structure of real IC systems, and the performance of a Booth multiplier would be mainly determined by partial product issues, e.g., multiplication and addition, as well as the frequency of the clock. Then, one of the potential improvements would be the asynchronous control to reduce power by cancelling the global clock, the other be the structure and implementation of the algorithm for high performance, and the last could be the benefits of reconfiguration for sharing process elements. In this paper, we proposed a Booth algorithm which organized by an asynchronous NoC, e.g., the partial product generators are located into a configurable network, and other part of the circuit are organized and adjusted by an asynchronous mechanism. The design is finally implemented by an 8-bit asynchronous Booth multiplier, which is synthesized and post simulated with a Xilinx Virtex-7 FPGA development board.

Density functional theory conjugated with non-equilibrium Green's function-based first principle approach is used to determine the ferromagnetic-doping effect in the current–voltage characteristics for the heterojunction biomolecular analytical structure. The quantum-mechanical transport phenomenon and multiple switching activities associated with sequential negative differential resistance properties have been observed for this adenine-thymine chain. The authors investigate the quantum-transport properties of conventional doping effect for ferromagnetic atoms in this bimolecular chain. The results show an electronic enhancement effect in quantum-ballistic conductivity for this chain along with sequential switching property. Among these ferromagnetic metals, Nickel shows significant transmission spectrum, sharp and prominent highest occupied molecular orbital (MO) and lowest un-occupied MO peak along with maximum quantum-ballistic current at room temperature. It is observed from the device density of states that large numbers of conducting channels are available for Nickel doping. This ensures high quantum-transmission current flow within the central molecular region for these ferromagnetic dopants. Compared to Iron and Cobalt, the current has been enhanced up to 4.05 times for Nickel dopant. High doping concentration (13.3%) has been introduced for this ab-initio model. It has found that the number of total switching process is increased during ferromagnetic doping mainly for Cobalt and Nickel dopants.

This study describes the highly-digital 4-bit 200 MS flash analogue to digital converter (ADC) whose major part can be digitally synthesised thus achieving low power, reducing the time-to-market and is scalable with technology. The comparators used in the ADC consist of complementary metal–oxide–semiconductor (CMOS)-based inverter and NAND-NOR as standard cells. The complete flash ADC is designed in 180 nm CMOS technology with 1.8 V supply with the power consumption of 4.51 mW. The signal-to-noise and distortion ratio, signal-to-noise ratio and spurious-free dynamic range are equal to 23.3, 25.2 and 30.1 dB. It provides an effective number of bits equal to 3.5. The differential non-linearity (DNL) of this ADC is ± 0.25 LSB and integral non-linearity (INL) is + 0.6 LSB.

Analogue-to-digital converter (ADC) is a very important circuit element to convert analogue signal into digital signal for information processing. There are several designs to implement ADC. The precision of an ADC depends on its resolution. In this work, this group has shown the design of eight-bit ADC using quantum dot gate non-volatile memory (QDNVM). The controllable threshold voltage of QDNVM is very useful to design comparators which are the main component of this ADC circuit. This work shows the use of QDNVM in eight-bit ADC design.

Differential power analysis (DPA) method is frequently used for the non-invasive side-channel attack to hack into the system. This study proposes a novel DPA immune design of basic gates, which show the dense distribution of autocorrelation and strong salience strength around 60%. The design has a highly regular structure with exactly similar evaluation path for both differential outputs, AND–NAND, and OR–NOR which can be easily extended for n-bit inputs. The design effort is minimal as the structure is such that AND–NAND design can be used to obtain OR–NOR function by just changing the placement of inputs. These gates have 0.46× less propagation delay, and 3.7× higher power consumption in comparison to other published work. The designs are simulated using Cadence tool with TowerJazz CMOS 180 nm technology with a power supply of 1.8 V.