In this work, design technique and analysis of low-energy consumption successive approximation register (SAR) analogue-to-digital converter (ADC) is presented. A dual capacitor array (CA) generates a digital-to-analogue reference voltage with increased accuracy. The CA supports multiple parallel operations to enhance conversion speed. Unit sized capacitors in CAs are few in number and present good capacitance density, thereby providing area efficiency and ease of routeing. A 9-bit SAR ADC using the proposed dual CA, implemented in a 90 nm CMOS process, has a small core area footprint of 0.00371 mm². At a 1 V supply and 100 kS/s, the ADC achieves a signal-to-noise and distortion ratio of 53.55 dB and consumes 0.47 μW, resulting in a figure-of-merit of 14.5 fJ/conversion step.

This study presents a new low-voltage and low-power, mixed-mode, universal Gm-C filter capable of generating simultaneous filtering outputs. The proposed circuit employs only 19 inverters as operational transconductance amplifiers, and 2 grounded capacitors in carbon nanotube field-effect transistor (CNTFET) technology. However, due to the proper use of subthreshold transistors biased at ±0.25 V supply, the power consumption of the proposed circuit is reduced effectively. Furthermore, as the HSPICE simulation results show, the proposed filter consumes only 11.66 µW of power, while its total harmonic distortion is obtained −55.4 dB at 100 MHz centre frequency. Moreover, the input referred noise values at 100 MHz are reduced to 11.57 nV/ and 760 fA in voltage and current modes, respectively.

This study presents a novel low-pass continuous-time filter based on the voltage flipped-source-follower (SF). The filter efficiently operates in CMOS 28 nm and improves the SF filters state-of-the-art thanks to a dedicated circuit that operates in fully-differential fashion (instead of the pseudo-differential typically used in state-of-the-art SF filters) with a dedicated Common-Mode-Feedback circuit. Thus this work extends the application of the SF filtering stages to the nm-range technologies where threshold voltage (V _TH) is only two times lower than the supply voltage (V _DD) for what regards standard-process MOS transistors. In order to validate the design concept, the proposed filter has been designed in CMOS 28 nm technology. Extensive simulation results of a 131 MHz −3 dB frequency proof-of-concept second-order filter are proposed. The device consumes 510 µW power from a single 1 V supply-voltage. In-band integrated noise is 160 µV_RMS and IIP3 is 19 dBm for 20 and 21 MHz input tones frequencies. Simulation results lead to 166 J⁻¹ figure-of-merit, outperforming the analogue filter state-of-the-art.

Some neurons like neocortical pyramidal neurons adapt with multiple time-scales, which is consistent with fractional-order differentiation. The fractional-order neuron models are therefore believed to portray the firing rate of neurons more accurately than their integer-order models. It has been studied that as the fractional order of differentiator and integrator involved in the neuron model decreases, bursting frequency of the neurons increases. The opposite effect has been observed on increasing the external excitation. In this study, integer- and fractional-order Hindmarsh–Rose (HR) neuron models have been implemented using sinh companding technique. Besides, the application of the HR neuron model in a simple network of two neurons has also been considered. The designs offer a low-voltage and low-power implementation along with the electronic tunability of the performance characteristics. Due to the use of only metal-oxide semiconductor (MOS) transistors and grounded capacitors, the proposed implementation can be integrated in chip form. On comparing with existing implementations, the implemented fractional-order and integer-order models show a better performance in terms of power consumption, supply voltage, order and flexibility. The performance of the circuits has been verified using 130 nm complementary MOS (CMOS) technology process provided by Austrian Micro Systems using HSPICE simulation software.

Low-power consumption has become an important aspect of processors and systems design. Many techniques ranging from architectural to system level are available. Voltage scaling or frequency boosting methods are the most effective to achieve low-power consumption as the dynamic power is proportional to the frequency and to the square of the supply voltage. The basic principle of operation of aggressive voltage scaling is to adjust the supply voltage to the lowest level possible to achieve minimum power consumption while maintaining reliable operations. Similarly, aggressive frequency boosting is to alter the operating frequency to achieve optimum performance improvement. In this study, an aggressive technique which employs voltage or frequency varying hardware circuit with the time-borrowing feature is presented. The proposed technique double samples the data to detect any timing violations as the frequency/voltage is scaled. The detected violations are masked by phase delaying the flip-flop clock to capture the late arrival data. This makes the system timing error tolerant without incurring error correction timing penalty. The proposed technique is implemented in a field programmable gate array using a two-stage arithmetic pipeline. Results on various benchmarks clearly demonstrate the achieved power savings and performance improvement.

This study proposes a single bit-line and disturbance-free static random-access memory (SRAM) cell for ultra-low voltage applications. SRAM cell with read-decoupled and cross-point structure addresses both the read-disturb and half-select stability issues; nevertheless, the write-ability is degraded due to the stacked pass transistors. In this study, the authors propose a single-ended 8T bit-cell and dual word-line control technique that can simultaneously improve the read stability, half-select stability, and write-ability without additional peripheral circuits, which is advantageous for bit-interleaved ultra-low voltage operations. A 4 kb test chip was implemented in a 90 nm complementary metal–oxide–semiconductor process to verify the proposed design. Silicon measurements indicate that the proposed design can operate at a voltage as low as 360 mV with 2.68 μW power consumption.

A multiphase all-digital crystal-less clock generator (CLCG) with an interpolating digital controlled oscillator (DCO) that achieves an operating frequency of 500 MHz with 10-phase outputs is proposed. The CLCG adopts a specific temperature coefficient of a time-to-digital convertor (TDC) to create a positive or negative temperature coefficient and compensates for the DCO frequency drift. A time amplifier (TA) can extend the timing resolution of the TDC and reduce the effects of process variations in order to tune the TA gains. The frequency compensator adopts the frequency difference between the ring oscillator and DCO to reduce the frequency drift. The frequency accuracy is 69 ppm/°C from  − 20 to 80°C. The root mean square jitter and output phase noise are 3.86 ps and − 100.36 dBc/Hz at 1 MHz, respectively. The core area of the test chip is 350 × 420 μm² in a 65-nm CMOS process. At a supply voltage of 0.6 V, the power consumption is 1.8 mW for the 5 Gb/s clocking system.

Digital calibration schemes generally allow for high-speed operation and reduced power consumption at the price of lower accuracy compared with their analogue counterparts. However, in dynamic comparators, when exceeding 4 or 5 bits, any resolution increase will be progressively traded against the circuit parameters. This study presents a three-step design procedure to optimise the comparator performance for a given N. First, a new configuration of the latch comparator has allowed optimising the comparison speed in terms of N. Second, the calibration scheme has been reduced to a simple digital sequencer to perform a progressive capacitive offset trimming. Third, the sequencer automatic increment has been programmed to stop at optimal operation to achieve the best calibration accuracy. The proposed method has then been applied to design a latch comparator with 7 bit calibration control in a commercially available 0.18 µm complementary metal–oxide–semiconductor technology. Post-layout statistical simulations have shown that the circuit can achieve up to 5.9 bit calibration resolution without altering the comparator performances.

In this study, parasitic elements (non-idealities) effect on a low-power DC–DC buck–boost converter design is analysed and investigation is carried out by both large (i.e. steady-state) and small signal analysis. The large signal analysis of non-ideal buck–boost converter explored the significant information such as nearly accurate duty cycle, maximum allowable duty cycle and maximum possible output voltage. Further, accurate mathematical design formulae are derived of inductor and capacitor for specified inductor current ripple and output voltage ripple (OVR), respectively. Moreover, consequences of different equivalent series resistance of capacitor on OVR is examined. Subsequently, the exact model of buck–boost converter is procured from the small signal analysis, which is almost analogous to practical system. In order to show the impact of non-idealities on controller design, an internal model control PID controller is designed for ideal, semi-non-ideal and complete non-ideal systems based on their respective models, which shows the controller based on non-ideal model provides very close results to practical system. Conclusively, the complete theoretical explorations are justified by simulations and substantiated by experimental results.

Design of DC–DC converter for harvesting maximum power from the multiple piezoelectric energy harvesters is a challenging task. In this work, a method to obtain maximum power from the multiple piezoelectric energy harvesters for supercapacitor charging is proposed. The method involves acquiring energy from each harvester by time-multiplexed operation of the multi-input buck–boost converter. The maximum power from each harvester is extracted by operating the converter to match the impedance of each harvester to the load impedance. The impedance matching is done by operating the converter with optimal duty cycle. The proposed method is experimentally evaluated, and the charging rate of supercapacitor is found to be higher while charging by the proposed method as compared to charging directly through the rectifier. The proposed method involves a single converter circuit for extracting energy from multiple piezoelectric energy harvesters, so that the component utilisation and its associated losses are very much reduced.

This study provides a comprehensive treatment of the design techniques of all-digital arithmetic units for time-mode signal processing. The arithmetic units investigated include time polarity detectors, time absolute-value generators, time adders, time baluns, time amplifiers, time quantisers, time registers, and time integrators. The principle, circuit implementation, constraints and limitations of these units are investigated in detail. An emphasis is given to time adders and time integrators. An in-depth study of time adders constructed from switched delay units, dual discharge paths, and unidirectional gated delay lines is provided. It is followed with the presentation of three time registered evolved from these time adders. Three time integrators developed from the preceding time adders and time registers are studied and their characteristics are compared. Finally, the design of a first-order time-to-digital converter utilising these arithmetic units is presented.

A multiplier is one of the key hardware blocks in most of the processors. Multiplication is a lengthy, time-consuming task. Vedic multiplication in field programmable gate array implementation has been proven effective in reducing the number of steps and circuit delay. Conventionally at the circuit level, complementary metal oxide semiconductor (CMOS) logic is used to design a multiplier. In CMOS circuits, the area is always an issue. Gate diffusion input (GDI)-based logic has been explored in the literature to reduce the number of transistors for various logic functions. Thus, Vedic mathematics, on the one hand, simplifies the multiplication process and reduces the delay; while on the other hand, GDI technique helps in minimising the transistor count (TC) and reduction in power. Therefore, this study puts forth a GDI logic-based 4-bit Vedic multiplier. To study the effectiveness of the GDI logic, the transient response of a 2-bit Vedic multiplier using CMOS and GDI is compared. For the 4-bit Vedic multiplier, two design approaches are taken into consideration. The performance of these circuits is analysed in terms of average power dissipation, delay, and TC. The effect of supply voltage scaling is also studied. The circuit simulations are carried out at 130 nm for bulk metal oxide semiconductor field effect transistor predictive technology model-based device parameters.

This study proposes a Manchester-encoded data transmission circuit suitable for 13.56 MHz radio-frequency identification (ID) tags integrated by indium–zinc–oxide thin-film transistors (TFTs). All the modules in the circuit are only constructed by two types of logic units: NOT gate and NOR gate. The 16 bit ID data are stored in the read-only-memory circuits realised by a fixed TFTs array. The 16 bit ID data are encoded by Manchester module as the output of the Manchester-encoded data transmission circuit with a bit rate of 103 kbps. The chip area is 6.5 mm² with the total number of gates as 76 and the sum of the transistors as 300. Moreover, the power consumption is 3.8 mW at VDD = 5 V.

Accurate dynamics of power converters are necessary to achieve good control performance. In this study, the dynamical model of the DC–DC buck converter is identified by the relay feedback method. The relay is connected in the closed loop to produce a limit cycle output. The important information of the oscillatory output is used for the identification. The relay is approximated using dual-input describing function (DIDF) in the mathematical modelling. DIDF can handle symmetric and asymmetric limit cycle outputs. The converter is modelled as a second-order plus dead-time system. Using the gain and phase angle criteria, analytical expressions are derived to estimate the dynamics. The converter dynamics obtained from the proposed method are compared with that estimated using the state-space averaging method. The model is also identified from the real-time experiment. To check the efficacy of the identified model, a model validation test is performed.

In this study, a real-time temperature compensation control system for tunable high-Q cavity-based filters are designed, implemented, and experimentally validated. Both bandpass (BPFs) (700–1000 MHz) and bandstop filters (BSFs) (1300–1600 MHz) with high-Q () resonators are monitored in real time to compensate for any temperature variations. The monitoring scheme includes additional resonators that share the same tuning piezoelectric actuators with the resonators of the radio frequency (RF) filters. An oscillator is coupled with each monitoring resonator resulting in an output signal at a frequency directly linked to the RF resonance. Each monitoring resonator is controlled by a user-provided input through a closed-loop in real time. The presented system is capable of compensating for temperature variations in the and range. The average system resolution varies from 0.23 to 9 MHz, depending on temperature, with a 1 ms sensing period. The closed-loop frequency shift is 6.5 MHz (0.93%) and 8.75 MHz (0.65%) for the BPFs and BSFs, respectively, in the to temperature range. This is to be compared with the open-loop change of 256 MHz (36%) and 590 MHz (44%) for the same temperature change. The monitoring oscillator power leakage to the RF cavities is optimised and measured to −101 dBm.

This study presents an improved convergent distributed arithmetic (DA)-based low complexity pipelined least-mean-square filter. The concept is based on a convex combination of two adaptive filters (ADFs) where the convergence performance of the combined filter is adjusted by the step-sizes of ADFs. The proposed technique replaced two ADF units by a single unit of the DA-based ADF. Further reduction in hardware complexity is achieved by sharing the filter partial products. Moreover, a bit-level coefficient update unit is employed to minimise its hardware complexity. In addition, a novel low-cost strategy is presented to improve the convergence performance of the proposed filter by comparing the time-window corresponding to the maximum correlation of delayed error signals with a pre-defined window with n being time instant and . Compared with the best existing scheme, the proposed design offers 46.42% fewer adders, 36.69% fewer registers and 18.75% fewer multiplexers for a 64th-order filter. Application specific integrated circuit synthesis results show that the proposed design occupies 37.10% less chip-area and consumes 24.79% less power. In addition, the proposed design provides 20.35% less area-delay-product and 4.76% less energy-per-sample for 64th order with the fourth-order base unit over the best existing scheme.

A comparative study on characteristics and performance of optical ring resonator architectures, i.e. circular, racetrack, and triangular-shaped optical resonators, have been carried out here. Constituent material used for designing these resonators is an silicon on insulator wafer consisting of thin silicon (Si) layer on silica (SiO₂) layer carried on a thick Si substrate having group index of 2.379. All the resonators are so designed that all provide equal free spectral range (FSR) of 25.2 THz. All these double-ring architectures have been analysed using delay line signal processing technique in z-domain and Mason's gain formula. FSR expansion has been achieved employing the Vernier principle. Various performance defining parameters have been also investigated.

A 135 nm gate length-based low noise enhancement mode N-polar double deck T-shaped gate Gallium Nitride (GaN) Metal Oxide Semiconductor (MOS)-high electron mobility transistor with double insulating layer of high-k dielectrics ZrO₂/HfO₂ is proposed. The device exhibits maximum transconductance of 0.55 S/mm, maximum drain current density of 1.4 A/mm and minimum noise figure (NF_min) of 0.72 dB at 20 GHz. A compact model for Two Dimensional Electron Gas (2DEG) density is developed by explicit solution of surface potential and Fermi level by considering first two sub-bands of triangular quantum well without using any numerical methods. Based on the surface potential drain current, intrinsic charge, gate capacitance, small signal and thermal noise models are developed. To validate the proposed numerical model, the results are calibrated with TCAD device simulation results and available experimental data from literatures.

This study presents a novel square/triangular wave generator based on multiple-output current follower differential input transconductance amplifier (MO-CFDITA) with reduced complexity in terms of transistors. The proposed generator comprises of single MO-CFDITA and one grounded capacitor only which makes the proposed generator circuit suitable to integrated circuit implementation. The proposed generator provides output square wave in current mode and output triangular wave in voltage mode. The amplitude of current-mode square wave is electronically and independently tunable via bias current. The DC level of the triangular wave is also electronically adjustable. The proposed generator has dual-slope operation and its duty cycle is adjustable with the help of DC current source over a range of 5–95%. The proposed generator consumes a power of 1.45 mW only and it is usable up to 50 MHz which is quite good operating frequency range. To examine the performance of the proposed generator, the cadence VIRTUOSO simulation results have been depicted. Additionally, the simulation results and performance parameters of complementary metal–oxide–semiconductor (CMOS) MO-CFDITA are included. The practicality of the proposed generator is verified through the experimental results.