Nanoscale complementary metal–oxide–semiconductor (CMOS) circuit design extensively employs multifinger layout technique to alleviate the performance degrading parasitic and mismatch effects that are typically observed with single-finger layout. However, a continuous increase in the number of fingers accompanied by a simultaneous decrease in their finger width could lead to the penalty of a higher degree of variation in the MOSFET's small-signal parameters. It is due to the heightened shallow trench isolation (STI) stress that gets developed in such devices. The optimisation of circuit performance with the arbitrarily fixed number and width of fingers would be ambiguous. In this work, an analysis of current–voltage (I–V) characteristics of a MOSFET as a function of number of fingers has been proposed. It was found that both the drain current and gate transconductance get affected by the number of fingers. The authors proposed a Miller-compensated two-stage [operational transconductance amplifier (OTA)] and common source amplifier by considering STI effect. It is also found that the parameters of the proposed design matched well with the set of desired specifications. Also, the area of multifinger MOSFET OTA is lowered by up to 60% relative to that from the conventional. All post-layout simulations were performed using standard UMC 65 nm CMOS technology.

A mixed-signal baseband demodulator for IEEE 802.15.6 impulse-radio ultra-wideband (IR-UWB) wireless body area network (WBAN) energy detection-based receiver is presented. It considers M-ary pulse position modulation (PPM) signalling format conforming to the IEEE 802.15.6 WBAN standard. The demodulator utilises ‘integrate-and-digitise’ approach employing simple mixed-signal circuits. The design is implemented in 0.18 μm CMOS technology operating at 1.8 V supply. The demodulator consists of a mixed-signal windowed integrator, a single-ended successive approximation register analogue-to-digital converter followed by a digital back-end. Further, its performance evaluation is carried out for 2-ary and 16-ary PPM signalling in different WBAN channels.

This study presents a new placement and routing method for analogue integrated circuit layout generation based on an evolutionary algorithm, which is called modified cuckoo optimisation algorithm. Layout parasitic effects are taken into account to ensure that the performance of the circuit is not deteriorated. In order to verify the performance of the proposed method, layouts of three different circuits including differential to single-ended amplification stage, two-stage and three-stage operational amplifiers (op-amps) are automatically generated in a 0.18 μm CMOS process with a 1.8 V supply voltage. The simulation results show the efficiency of the proposed algorithm in the analog layout generation.

This paper presents reconfigurable and hardware-efficient VLSI architecture of time domain cyclostationary-feature detector (TCD) for spectrum sensing in the cognitive-radio wireless network. It incorporates new architecture for autocorrelator that supports the entire range of subcarriers used by orthogonal frequency division multiplexing signals compliant to 4G LTE-Advanced wireless network. A novel scheme of overflow/underflow protection is proposed for the coordinate rotation digital computer engine of TCD. Additionally, hardware-efficient techniques have been introduced for the multiply-&-accumulate and accumulator architectures of suggested TCD design. Real-world signals are captured using universal software radio peripheral devices and are fed to its FPGA prototype. An application specific integrated circuit synthesis and post-layout simulation of the proposed detector have been performed using 65 nm-CMOS technology and it occupies 0.32 mm² of core area and consumes total power of 18.5 mW at 100 MHz clock frequency. In comparison with the state-of-the-art works, the proposed detector requires 34 and 93% lesser hardware resource and memory, respectively

This study theoretically analyses the performance of multiple quantum well infrared photodetector mainly with the variation of active layer doping. However, the effect of temperature and applied bias has also been studied. Results show that the effect of doping on the responsivity is significant whereas on the dark current is less significant. Effect of temperature on the dark current is more significant compared with that of doping concentration. Moreover, concerning the detectivity of the device, choice of doping plays a significant role on the detector.

This study presents a three-dimensional (3D) analytical model of triple material tri-gate silicon-on-nothing metal–oxide–semiconductor field-effect transistor. The performance of the device by varying the different device parameters as well as the device's immunity toward the various short channel effects such as Drain-induced barrier lowering (DIBL), hot carrier effect, threshold-voltage roll-off and subthreshold swing are investigated. The 3D Poisson's equation with appropriate boundary conditions is solved considering the parabolic potential approximation method to obtain the surface potential distribution. In addition, the calculations for threshold voltage and electric field are also done and the results obtained are verified using a 3D device simulator, namely ATLAS from SILVACO.

Finding the best possible word length to accuracy trade off seems to be an obvious design task. However, the literature and carful design reviews show that word lengths are often overestimated to put the data accuracy at the safe side. This study proposes a mathematical process to balance that trade off. It describes an analytical optimisation technique that considers every interconnection and it shows clear improvement with respect to published results. To allow reproducibility of their work, detailed procedures are provided. Implementation results are presented for different configurations of infinite impulse response filters. More, the impact of the proposed bit-width optimisation on the filter poles and zeros is provided to show the effectiveness of the proposed solution. Their solution provides overall improvement going up to 17% of the circuit's area with respect to existing methods. The proposed technique for uniform fractional bits allocation runs in a negligible time independently of the targeted accuracy.

This paper treats the s-parameter performance degradation by hot electron induced for N-MOSFET devices used in radar applications. This study is relevant for devices operating in the RF frequency regime. The power LD-MOSFET device (0.8 µm channel length, Gate oxide thickness 0.065 µm and 2.2 GHz) are designed and fabricated. Subsequently, life tests in pulsed RF cause, after ageing, the electrical behaviour and its relation with charge trapping at the interface are presented and discussed. Unlike all other current methods, a complete evaluation of S parameters is carried out to obtain key information concerning the defects location. The s-parameter performance degradation can be explained by the transconductance and the miller capacitance move, and by the leakage current augmentation IG, which is shown by hot-carrier event from the Si/SiO₂ interface state generation and/or in a build up of negative charge. Also, the degradation can be predicted by the experimental correlation of RF and dc performance shifts, favour by the measurement of dc performance or initial leakage current. The analysis accompanied proves that the s-parameters shift by hot electron induced and should be taken into consideration in the design. Through physical processes of ATLAS-SILVACO simulations these degradation phenomena are located and confirmed

As one of the most widely used memristor models, the spintronic memristor has become a promising candidate for the electronic synapse. Non-volatility, nanoscale geometries, binary data and multi-level information storage make the circuit simpler and consume less electricity. In this study, a new spintronic memristor synaptic circuit is proposed which can realise positive, zero and negative weights successfully. Furthermore, the circuits of the presented synaptic-based neuron and compact neural network are designed and an improved random weight change (RWC) algorithm is proposed. Compared with the traditional RWC algorithm, it has faster training speed and less training error. In addition, the neural network is applied to data prediction, the result of which is closer to real data. Finally, the correctness and effectiveness of the proposed network are verified via a series of computer simulations.

Through-silicon vias (TSVs) are a key technology for three-dimensional integrated circuits. As the integration of circuits increases, high temperature has a greater effect on the performance of the TSV interconnections. The metal–oxide semiconductor (MOS) effect is one of the most important temperature-dependent characteristics of a TSV. This study introduces the mathematical model of a TSV to predict the MOS effect more accurately. The thermal effect that varies due to the change in the TSV capacitance and depletion region can be modelled by the non-linear the Poisson equation including mobile charge carriers. In procedures to solve this equation, the proposed method considers not only the thermal effect of intrinsic carrier concentration and silicon bandgap energy but also the shift effect of the flat band voltage due to the Si–SiO₂ interface charges. In addition, since it considers the minority carrier generation rate, which is dependent on the change of gate voltage, the MOS effect in a TSV can be explained more accurately using equations derived from these procedures. To verify the proposed mathematical model, comparison with the numerical method is carried out, and these results show that the proposed method is very accurate in explaining the MOS effect in a TSV.

An optimal quantum-dot cellular automata (QCA) design for full adder (FA) based on an optimal three-input exclusive-OR (XOR) gate is presented. This XOR structure utilises a new configuration of cells unlike traditional gate-level approaches. The coplanar QCA FA spans over and delays of 0.5 clock cycles with 40 cells. It achieves total energy dissipation as low as 0.144 eV at 1.5 energy level. The utility of proposed gate is leveraged to design a ripple-carry adder (RCA) as a specific application. For performance evaluation, the authors use traditional cost metrics and QCA-specific cost function. Results show that proposed n-bit RCA outperforms most of the best state-of-the-art designs known in the literature. For example, cell count (area consumption) of 4, 8, and 16 bit adders is 62% (70%), 66% (84%), and 70% (86%) less than the best coplanar RCA design results. In addition, by taking the new cost metrics into account, it is found that proposed adder performs fairly well as compared to the previous adders too. These designs are realised and simulated using QCADesigner.

This study presents a wide tunable Gm-C low-pass filter for biomedical and wireless applications. The proposed filter was designed using the standard 90 nm complementary metal–oxide–semiconductor technology operating with a balanced supply voltage of 1.2 V. Modified linearisation techniques are used to improve the linearity of the digital programmable operational transconductance amplifiers (DPOTAs) which are used in the filter design. The proposed filter consists of three parallel fourth-order Butterworth sections. Each section is designed and optimised to target a specific band of frequencies. The operation of selecting between the different sections is free of any physical switches. Turning off the unwanted sections is utilised by setting the control bits of the corresponding DPOTAs to zeros. The performance of the proposed filter and DPOTAs is validated through simulation results. The third-order harmonic distortion of the DPOTA remains below −60 dB up to 0.5 V differential input voltage. The simulation results show that the digitally tunable cutoff frequency of the proposed low-pass filter is widely varied in the range of 114 Hz–12 MHz. The proposed filter achieves IIP3 of 28 dBm.

In this study, the authors propose the use of distributed elements interconnected with switches to construct a reconfigurable matching network (RMN). Several RMNs are constructed using tunable lumped elements. However, this technique increases the system complexity because of the use of digital-to-analogue converters and synthesis algorithms. In this study, the proposed RMN employs a non-uniform transmission line with adjustable characteristic impedances, which are controlled by opening or closing the switches. While previous studies on non-uniform transmission lines have aimed to investigate the fixed configurations, this topology is designed to be an RMN that satisfies the design challenges. The maximum dimension is 0.2 times the guided wavelength of the low operational frequency, and five switches are used; however, the matchable impedances cover an extensive range of the Smith chart, and the RMN successfully tunes inherently unmatched antennas to operate at a target frequency band that depicts a fractional bandwidth of 60%. Additionally, the evaluated results depict that the fabricated RMN illustrates low insertion loss and high transducer gain and that it achieves both antenna-mismatch compensation and antenna-bandwidth extension.

In high-density three-dimensional (3D) memory technology, a stacking method is used to create memory devices and access devices at the intersections of bit lines and word lines. For this application, access devices should have a high on/off ratio, high current density for writing cycles, and high endurance. Consequently, an arsenic–tellurium–germanium–silicon nitride compound (AsTeGeSiN) threshold switching device with a high current density of 10⁴ A/cm² above the threshold voltage (V _th) is reported as a good candidate for use in access devices. In addition, scaling down of access devices as well as memory devices is essential for high-density 3D memories. However, in AsTeGeSiN threshold switching devices, fast degradation by pulse cycling in smaller devices is observed. To find the main cause of fast degradation by pulse cycling in smaller devices, the low-frequency noise properties are examined. The rapid increase in the trap density (N _T) in small devices is the main cause of fast degradation by pulse cycling in AsTeGeSiN devices. On the basis of this evaluation, the author examines the effect of annealing temperature and annealing time on the pulse endurance in smaller devices. Using an annealing temperature of ∼600°C improves the cycling endurance of smaller devices.

The emulation of low-loss or lossless one-dimensional (1D) or 2D transmission mediums using analogue sampled-data signal processing is presented. Based on discrete-time wave propagation simulation, transmission lines are emulated with many elementary identical delay elements, implemented by simple equivalent switched-capacitor (SC) circuits. The accuracy and limitations of this discrete time model are studied in the frame of power network fault location using electromagnetic time-reversal principle. The sensitivities to non-ideal effects usually plaguing analogue CMOS SC circuits, such as amplifier finite open-loop gain, offset, and parasitic charge injection due to clock feedthrough, are evaluated in the same context. It is shown that the SC line emulation is well suited to the presented fault location technique and considerably reduces the fault location time (by a factor up to 100) in comparison to standard digital solutions, allowing fault location resolutions of typically 1% within a few hundred milliseconds. These expectations are confirmed by measurements realised on the presented line model integrated-circuit, implemented in an AMS 0.35 μm CMOS process. The speed improvement obtained through the presented method is essential, potentially allowing real-time fault management in power grids.

In this study, a variable gain low noise amplifier (VG-LNA) working at X band is designed and simulated in 65 nm complementary metal oxide semiconductor technology. A two-stage structure is used in the proposed VG-LNA. Besides, the current-reused technique causes a higher gain without consuming extra power. As an on-chip voltage (V _cnt) is changed, the gain continuously and almost linearly varies. The highest gain is 27.8 dB that can be reduced to 8.3 dB almost linearly and continuously as the control voltage is increased. The lowest value of S11 is −28.2 dB at 10 GHz. Also, NF is <2.75 dB at the operating frequency range; while NF_min = 1.8 dB. The highest value of third-order intercept point is 2.03 dBm that always remain larger than −10.1 dBm. The basic advantage of this structure in comparison with other similar works is that not only the key parameters remain fixed with reduction of gain, but also the operation range of V _cnt is widened from 0.3 V to V _dd in order to extend the gain control range to 19.5 dB. Moreover, these results are achieved in a situation that the proposed VG-LNA draws only 3.9 mA from a 1.2 V.

Emerging nanoscale computing structure quantum-dot cellular automata (QCA) is evolving as a possible replacement for complementary metal–oxide–semiconductor technology in near future. Being a new technology, it is prone to various types of fabrication-related faults and process variations. So, QCA-based circuits are prone to errors, and therefore pose significant reliability-related issues. Hence, there is an emerging need to design fault-tolerant QCA-based circuits to mitigate the reliability issues. This study first presents QCA-based new designs of 2-input Exclusive-OR gate and 1 bit full adder using conventional design approach without redundant QCA cells. Then, the fault tolerance has been implemented in these designs by introducing redundant QCA cells. The proposed circuits exhibit significant improvements in fault-tolerant capability against cell omission, misalignment, displacement, and extra cell deposition defects. The proposed fault-tolerant designs have been compared with existing designs in terms of generalised design metrics of QCA circuits. Energy dissipation results have been computed for the proposed fault-tolerant circuits using accurate QCAPro power estimator tool. Influence of temperature variations on the polarisation of the proposed fault-tolerant circuits has also been investigated. The functionality of the proposed circuits has been verified with QCADesigner version 2.0.3 tool.

Network-on-chip (NoC) adopted for many-core intercommunications may face long link delay and power consumption limitations. A proven solution is to segment long links with storage elements or repeaters. Besides, a new design paradigm called elastic has been considered in the literature, which seems suitable for NoC designs. In this study, the authors explore the benefit of various elastic-buffer (EB) structures to be used for link pipelining. They study elastic handshaking protocols and explore various elastic buffer designed to be used in NoC era. They propose to use synchronous elastic flow (SELF) handshaking protocol for link pipelining. Results show elastic buffer structure based on SELF-handshaking protocol, which can run at least with 21% higher frequency, has 25% less delay and consumes 8% less power compared with other proposed designs. They have explored the process variation issues with various scenarios on seven different structures. They have improved the SELF-elastic buffer, which is more resilient against process variation, proposing two new structures. The new proposed structures exhibit about 5% better performance and 13% less power delay product variation in average.

This work studies the transient responses and steady-state ripples of digital low dropout (LDO) voltage regulators. Simulation models as well as closed-form expressions are provided for estimating the LDO output settling behaviour after load current or reference voltage changes. Estimation equations for the magnitude and frequency of LDO output steady-state ripples are also presented. The accuracy of the developed models is verified by comparing estimation data with results obtained from circuit simulations. The use of the developed estimation equations in design space exploration is also demonstrated.

For cryptographic applications, such as DSA, RSA and ECC systems, the crypto-processors are required to perform modular multiplication (MM) on large integers over Galois field. A new digit-serial MM method is presented by using a variable size lookup table. The proposed modular multiplier can be designed for any digit-size d and modulus M which only requires simple operations such as addition and shifting. Based on theoretical analysis, the efficient digit-serial MM architecture requires the latency of clock cycles. As a result, the developed architecture can achieve less area–delay product on hardware when compared with previous designs.