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Online ISSN 1751-8598 Print ISSN 1751-858X

access icon free IET Circuits, Devices & Systems

Volume 12, Issue 5, September 2018

Volume 12, Issue 5

September 2018

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    • Design procedure for multifinger MOSFET two-stage OTA with shallow trench isolation effect
      Mixed-signal demodulator for IEEE 802.15.6 IR-UWB WBAN energy detection-based receiver
    • Placement and routing method for analogue layout generation using modified cuckoo optimisation algorithm
      Hardware implementation and VLSI design of spectrum sensor for next-generation LTE-A cognitive-radio wireless network
      Effect of doping on the performance of multiple quantum well infrared photodetector
      Analytical modelling and performance analysis of gate engineered TG silicon-on-nothing metal–oxide–semiconductor field-effect transistor
      Precision analysis with analytical bit-width optimisation process for linear circuits with feedbacks
      Symptom reliability: S-parameters evaluation of power laterally diffused-metal–oxide–semiconductor field-effect transistor after pulsed-RF life tests for a radar application
      Spintronic memristor synapse and its RWC learning algorithm
      Rigorous mathematical model of through-silicon via capacitance
      Efficient design of coplanar ripple carry adder in QCA
      An 114 Hz–12 MHz digitally controlled low-pass filter for biomedical and wireless applications
      Broadband reconfigurable matching network using a non-uniform transmission line
      Downscaling AsTeGeSiN threshold switching devices for high-density 3D memories
      High-speed analogue sampled-data signal processing for real-time fault location in electrical power networks
      Two-stage current-reused variable-gain low-noise amplifier for X-band receivers in 65 nm complementary metal oxide semiconductor technology
      Fault-tolerant design and analysis of QCA-based circuits
      Elastic buffer evaluation for link pipelining under process variation
      Digital LDO modelling techniques for performance estimation at early design stage
      Efficient digit-serial modular multiplication algorithm on FPGA

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