Classical DC current transformer, based on a linear amplifier as a compensating amplifier, is well known as a power inefficient device. If the linear amplifier is replaced with switching counterpart, significant power saving can be achieved. A natural choice for replacement can be found in a half-bridge class-D amplifier. However, the half-bridge class-D amplifier is prone to bus-pumping effect, and direct replacement cannot be performed in a straightforward manner. This study presents an analysis of power consumption issues and irregular behaviour for a DC current transformer, caused by the bus-pumping effect. For the case of DC current measurement, the main issues are explained, giving better insight into power consumption, and possible hazards to transformer circuitry. Presented analytical results are experimentally verified.

In this study, the design of concurrent penta-band capable antenna with integrated low-noise amplifier (LNA) for vehicular wireless communication applications is presented. Spiral structured penta-band-based planar monopole antenna is designed to cover navigational frequencies 1.2 and 1.5 GHz, wireless communication frequencies 2.4 and 3.3 GHz and dedicated short range communication frequency 5.8 GHz. LNA was designed and developed with pseudomorphic high electron mobility transistor technology, frequency transformation technique, and load–pull methodology that operates simultaneously at all desired frequencies. The designed antenna with integrated LNA helps better return loss and improved impedance bandwidth compared with passive antenna designs. The developed antenna module operates simultaneously at 1.2, 1.5, 2.4, 3.3, and 5.8 GHz with a gain >10 dB and noise figure <2 dB. More than 150 MHz impedance bandwidth achieved at all the desired bands with this proposed integrated antenna module with LNA.

This study reports a frequency-modulated ultra-wideband transmitter optimised for low-power consumption. The chip includes a sub-oscillator tunable from 0.1 to 4 MHz, a radio-frequency oscillator tunable from 3.0 to 4.5 GHz, and an output power amplifier with a matching network. Depending on the channel selected, the measured transmitter consumes between 440 and 640 μW of power to produce −14 dBm continuously to a 50 Ω load. Two power supplies are used to reduce the effect of wasted voltage headroom between circuit blocks. Fabrication is done using the International Business Machines Corporation 130 nm complementary metal–oxide–semiconductor technology on a 1 mm × 1 mm loose die, the circuit occupies 0.2 mm².

A novel fault tolerant delay cell for ring oscillator (RO) is proposed. As RO is one of the crucial blocks in phased locked loop, delayed locked loo and clock data recovery, it should be tolerated against single event transient (SET) and stuck at faults for harsh environment. Their proposed hybrid fault tolerant topology is combination of triple and quad transistors redundancy, which is applied to the delay cell structure based on the sensitivity role of each transistor. The simulation results with Cadence software show that the proposed fault-tolerant delay cell dissipates 34.34 µW power, while it occupies 127.2 µm² chip area. The proposed topology not only has lower power dissipation in comparison with existing fault tolerant delay cells but also is more reliable against stuck at single and multiple faults and also SETs. By using the proposed reliable delay cell in the RO, the achieved power dissipation and phase noise are about 249 µW and −96 dBc/Hz, respectively, while higher reliability is achieved in comparison with non-redundant RO s.

This study is focused on the experimental investigation of noise at microwave frequencies for scaled gallium arsenide high-electron-mobility transistor's (HEMT's). The light activation of noise has been achieved by laser exposure in the visible range. The devices have 0.25 μm gate length and 100–200–300 μm gate widths. Their DC characteristics, linear scattering and noise parameters were measured both in dark condition and under continuous wave light exposure in the 2–18 GHz frequency range. Previous results had shown a remarkable influence on all the above-measured parameters under illumination, with a special concern for the noise performance. Therefore, the authors investigated the origin of this light-activated noise in terms of the intrinsic noise sources, by extracting a noise temperature circuit model for each HEMT.In addition, the noise model formulation based on the P, R and C as well as the K _g, K _r and K _c coefficients is used to enlighten the key aspects of the optically activated noise on the device performance. It is observed that the degradation of the minimum noise figure can be attributed to the noise coefficient R, related to the gate noise source that is strongly affected by the charge generation related to light exposure.

In this study, a design technique for low-energy consumption and area-efficient successive approximation register analogue-to-digital converter (ADC) is presented. Digital-to-analogue conversion equivalent voltage is acquired utilising passive sharing of charge between two unit capacitors and integration of the shared charge onto an input sample-and-hold capacitor, via a switched capacitor integrator circuit. The architecture is less parasitic sensitive and low noise, yielding an area and energy-efficient ADC. To demonstrate the efficacy of the proposed technique, a ±350 mV 8 bit 0.78 MS/s ADC is designed in a 90 nm complementary metal–oxide–semiconductor process. The ADC core has a small area footprint of 0.00145 mm² and has a figure-of-merit of 11.39 fJ/conv-step.

A novel phase-locked loop (PLL) architecture including a composite phase frequency detector (PFD), two charge pumps, variable loop filter topology and voltage-controlled oscillator is proposed in this study. Composite PFD offers higher-gain and loop bandwidth (BW) during tracking when and provides a lower-gain and loop BW during tracking when as well as after lock-in. The PLL system is designed to ensure stability by maximising and equalising phase margin in both the linear as well as non-linear operations. The transfer characteristics of composite PFD are free from the blind zone and also found possible to eliminate glitches from the output. A prototype of PLL operating at 2.56 GHz developed on 180 nm complementary metal–oxide–semiconductor process is found to achieve reference spur of −71.4 dBc, lock time of 2.05 μs, peak-to-peak jitter of 3.412 ps, phase noise of −110 dBc/Hz at 100 kHz and final placement area of .

A new-type four-dimensional cellular neural network (CNN) is designed, whose piecewise linear function is replaced by smooth continuous function as CNN output module, theoretical analysis proves the new system has chaotic characteristics. By adding two cells, this study generates flux-controlled memristor and creates a brand new six-dimensional memristive CNNs. With the purpose of verifying the validity of this scheme, universal electronic components are adopted to build a memristive module and apply them to the integrity circuit of this system. Multisim circuit simulation software shows that this memristive module has the characteristic of the hysteresis loop as well, and circuit output curves are approximately in agreement with those of MATLAB numerical calculation results within the range of the permitted errors. Finally, via analyses of phase trajectories, equilibrium points, bifurcation diagrams, Lyapunov exponents, and dimension, this study demonstrates that this new type memristive CNNs possesses more abundant dynamic characteristics.

The authors focus on exploring the -embedding balanced truncation method of coupled systems. First, the coupled system is converted into a closed-loop system. Then, the -embedding technique and the Cholesky factor-alternating direction implicit algorithm are introduced to establish the balanced truncation method. The error bound and the stability of the resulting reduced-order system are discussed. Furthermore, the proposed method is applied to reduce the order of each subsystem such that the original interconnected structure is preserved. The error bound and the stability of the corresponding reduced-order system are also investigated. Finally, two numerical examples are employed to demonstrate the efficiency of the proposed method.

Here, the necessary and sufficient conditions for realisability of a general class of impedance functions by passive electrical networks composed of two fractional element (fractional capacitor or fractional inductor) and some resistors are found. Also, a systematic procedure is proposed to obtain such passive electrical networks in the realisable cases. Moreover, by establishing a connection with the previously reported researches on the subject of inerter-based passive mechanical control, further results on the maximum number of the resistors required for passive realisation are obtained. Furthermore, a numerical example is presented to show the usefulness of the paper achievements in passive realisation of impedance functions.

In this study, a novel level shifted version of flipped voltage follower (FVF) cell, which provides efficient class-AB operation, is presented. The level shifter is used to increase the swing of the FVF cell. In the proposed circuit, a bulk-driven metal–oxide–semiconductor field effect transistor is used as a current source to improve the sourcing capability and symmetrical slew rate for the class-AB operation. The circuit has a high-input/-output swing of 1.01 V/0.80 V, wide bandwidth of 751 MHz and low-output resistance of 107 Ω. The proposed circuit has been designed and simulated in a Cadence Virtuoso Analog Design Environment using BSIM3v3 180 nm complementary metal–oxide–semiconductor technology. The post-layout simulation results have also been presented to demonstrate the performance of the proposed circuit.

In order to find a way to solve the contradiction among storage space, transmission capacity and the data volume in the embedded systems, a data compression scheme based on block matching with an identifier is presented by using the technology of digital integrated circuit. The scheme can achieve lossless real-time data compression and reduce the volume of the data. Through statistical analysis on the data source, the authors can obtain that such a scheme has many advantages in real-time performance, a complication of implement, efficiency and practicability. So the digital circuit is considered as a method which can present the encoding process. With the help of QUARTUS II, they combine Verilog and schematic to finish the design hierarchically and code the decompression program by using C language for comparison. The accuracy and efficiency of the circuit are verified with simulation and relevant experiments. The average compression rate is 52.3% with 12 MHz clock frequency and the compression speed on average is 352% faster than the one by using block-match software algorithm. The scheme would have good performance in many embedded systems.