The Internet of Things paradigm considers the deployment in the environment of a profusion of heterogeneous sensor nodes, connected in a complex network, and autonomously powered. Energy harvesting is the common proposed solution to supply such sensors, and many different sources such as light, mechanical vibrations, temperature differences can be considered individually or in combination. Specifically, a thermoelectric generator (TEG), taking advantage of the Seebeck effect, is able to harvest electrical power from a temperature gradient of a few degrees. This study presents a chip fabricated in 130 nm CMOS technology, designed to convert a typical 50 mV output from a TEG into 1 V. The batteryless design utilises both halves of a 50% duty cycle clock. Measurements have been performed by using a TEG, and an equivalent TEG model, i.e. voltage source (50 mV–200 mV) with a series resistance of 5 Ω. The result shows that the proposed prototype can extract 60% (at 50 mV) to 65% (at 200 mV) of the total available power. The energy harvester can self-start at 50 mV with a 2.8 ms startup time, which is a significant improvement over the past work.

This study focuses on sensitivity of electronic circuit in low-voltage release to voltage sags based on a large-scale test results. Although studies about ride-through capability of some electronic devices during voltage sags have been carried out, there is few research available on sensitivity of electronic circuit in low-voltage release to voltage sags. Operation principle and working states of electromagnetic structure are discussed. Subsequently, a detailed test scheme is proposed based on latest standards and several kinds of 220 V low-voltage releases have been tested. Test results indicate that output waveform of electronic circuit under voltage sags can be classified into two types, which shows a clear correspondence with working state of electromagnetic structure and tripping condition of low-voltage release. Finally, six working modes are presented to analyse the relationship between output waveform of electronic circuit and the magnitude and duration of voltage sags in details.

Based on negative feedback technique, a complementary metal–oxide semiconductor (CMOS) voltage reference with ultra-low-power, low supply voltage and high-power supply rejection ratio (PSRR) is proposed and simulated using a 0.18 standard micrometre CMOS technology. The operating supply voltage ranges from 0.85 V to 2.5 V and the temperature ranges from −20°C to 80°C. The voltage reference can achieve a temperature coefficient of 16.3 ppm/°C and line sensitivity as low as 0.086 ppm/V, without the use of resistors or special devices, consuming 202 nA current at 27°C. Besides, the PSRR is only −113 dB at 1 Hz, −64 dB at 1 kHz, respectively.

Motion estimation (ME) is the most computationally intensive task in video encoding. This study proposes a full-search variable-block-size ME for the high-efficiency video coding or H.265 specification. The proposed method reduces memory requirements to a large extent by following a Morton order for data reading and a sum of absolute differences reuse strategy. The data bandwidth demand is also diminished by broadcasting data into multiple processing elements. This ME accelerator supports variable-block-size prediction blocks ranging from to , and is reconfigurable in various search ranges for a trade-off between performance and area. The proposed method for very-large-scale integration (VLSI) architecture is synthesized with 32 nm technology, and is capable of real-time encoding of ultra-high-definition (4K-UHD, at 30 Hz) video with a search range of 64 pixels in both horizontal and vertical directions, operating at a frequency of 282 MHz.

Configurable electronic devices have been developed to provide more flexibility in the advanced digital system design, which needs more device density and there by relies on device scaling. Besides, International Technology Roadmap for Semiconductor (ITRS) has predicted scaling limitation for conventional silicon (Si)-based devices. Researches on post-Si materials have proved that carbon could be one of the material which can replaced with Si. Owing to exceptional properties of graphene, designs with graphene-based devices can replace with Si based ones. This study proposes design and characterisation of graphene-based simple field-programmable gate array as a platform of configurable logic structure for future developments. This study focuses on design and characterisation of configurable logic block (CLB), flip-flop as internal sequential logic devices in CLB, and routing switch, which are designed using graphene nanoribbon field-effect transistor (GNRFET). The results indicate that proposed CLB is much faster than Si based one and power–delay product of proposed sequential element is much lesser than its counterpart in Si-based technology. In addition, the proposed GNRFET-based routing switch requires minimum count of 6 transistors to provide desirable functionality. Foreseeing the feasibility of architecture, this study suggests the possible layout of the proposed logic elements needed for CLB.

Modern microprocessors utilise embedded thermal sensors to continuously monitor the chip's temperature during runtime. However, the overheating locations change temporally and spatially depending on the various workloads running on the chip. Furthermore, on-chip thermal sensor readings are highly affected by noise due to fabrication fluctuations and randomness, which makes the task of thermal monitoring particularly challenging. In this study, the authors first establish overheating detection models to address the thermal sensor allocation problem under two different conditions when the on-chip thermal sensor observations are corrupted by noise. On this basis, a heuristic method based on genetic algorithm is proposed to find a near-optimal thermal sensor allocation solution, which can make overheating detection probability significantly improved with a greatly reduced execution time. They also propose a hybrid algorithm to identify the optimal thermal sensor placement for each individual chip block or component. Moreover, they develop an oil-based cooling system and utilise infrared thermal imaging techniques to capture the thermal traces of a real dual-core microprocessor when running various workloads. The experiments demonstrate that the authors’ proposed thermal sensor allocation methods obviously outperform several common allocation approaches in terms of overheating detection, which can provide an accurate and reliable thermal monitoring.

This study presents an efficient and high-speed very large-scale integration implementation of point multiplication on binary Edwards curves over binary finite field GF(2 ^m ) with Gaussian normal basis representation. The proposed implementation is a low-cost structure constructed by one digit-serial multiplier. In the proposed scheduling of point multiplication, the field multiplier is busy during point addition and point doubling computations. In the field multiplier structure, by using the logical effort technique the delay is optimally decreased and the drive ability of the circuit in the point multiplication architecture is increased. Also, to reduce area and number of transistors of the point multiplication circuit, all components are selected based on low-cost structures. The design is implemented in 0.18 μm CMOS technology over binary finite field GF(2²³³). The results confirm the validity of the proposed structure and its high performance in terms of delay and area cost.

In recent years, subquadratric-and-quadratric Toeplitz matrix–vector product (TMVP) computations are widely used for the implementation of binary field multiplication in elliptic curve cryptography. Pure subquadratric TMVP structure involves significantly less space complexity and long computational delay, while quadratric TMVP structure involves larger space complexity and less computation delay. To optimise the tradeoff between time and space complexities, this study presents a novel hybrid multiplier for Gaussian normal basis (GNB) in GF(2 ^m ) which combines subquadratic and quadratic structures. From the theoretical analysis, it is shown that the proposed hybrid multiplier can save ∼18% space complexity and 12% time complexity than the existing GNB multiplier with pure TMVP decomposition.

A 10-bit pipelined analogue-to-digital converter (ADC) at a sampling rate of 100 MS/s utilising only metal–oxide–semiconductor (MOS) transistors is presented and designed in 1.8 V 0.18 μm standard digital complementary MOS (CMOS) n-well technology. The internal gain of value 2 of the intermediate stages is achieved by using a charge-pump-based concept that avoids the use of power-area inefficient operational amplifier. All the capacitors are realised by capacitors implemented by metal–oxide–semiconductor field-effect transistors (MOSCAPs) that allows easy integration with any inexpensive standard digital CMOS technology, and altogether giving low area-power-cost solution. A low DC gain CMOS differential amplifier in source follower configuration is used and low gain effects are calibrated digitally in the background. Peak differential non-linearity (DNL) improves from −1/+0.27 least significant bit (LSB) to −0.43/+0.57 LSB and peak integral non-linearity (INL) is reduced from −9.56/+9.3 LSB to within range of ±0.5 LSB after calibration. Also signal-to-noise plus distortion ratio (SNDR) and spurious-free dynamic range (SFDR) increase to 65.4 and 72.08 dB, respectively, after calibration.

This study presents an architecture-optimising methodology for embedding an learning vector quantization (LVQ) neural network on an field programmable gate array (FPGA) device. The embedded architecture contains both learning and decision circuitry and is optimised towards the lowest power/energy consumption. The low-power/energy architecture is obtained through the selection of the best one amongst a number of architectures produced by FPGA software design tools that combine power, area and the ergonomic utilisation of internal FPGA resources. A complete characterisation of power at the architectural level was carried out using the Xpower tool. An analytical power model was determined by the following parameters: area, delay and LVQ topology. Concerning the authors’ architecture, there is a 28% gain in the area design. Moreover, it consumes 8% power in the nanoboard 3000 compared with the other ones.

This study presents the design and simulation of a fully differential two-stage op-amp in a 0.18 μm complementary metal–oxide–semiconductor process with a 1.8 V supply voltage. In this op-amp, positive feedback technique and split-length transistors (SLTs) are employed to increase the DC-gain of the op-amp by about 22 dB without affecting the unity-gain bandwidth (UGBW), stability, power dissipation and output voltage swing of the conventional two-stage op-amp. A comprehensive analysis is provided for differential-mode gain, common-mode gain, power supply rejection ratio, input-referred noise, input offset, frequency response and the effect of using SLTs on DC-gain sensitivity. The proposed op-amp is utilised in a flip-around sample-and-hold amplifier (SHA). The output spectrum of the SHA shows the total harmonic distortion of 0.0023%. The post-layout and Monte Carlo simulation results show that the proposed op-amp has better performance than the state-of-the-art designs.

This study presents a two-stage current source concept which features low-current noise, excellent drift and stability for higher operating currents. Generally, it is much easier to obtain higher stability and lower-noise parameters for small operating currents rather than large ones. This fact was used within this concept, where a precise low-current source (the second stage) corrects the fluctuations of high-current one (the first stage). In details the theory of operation for setup, the noise-sources analysis and measurement results are presented. For a maximum operating current equals 1 A, the current noise density of 126 nA/√Hz (at f = 1 kHz), long-term stability of ±2.1 ppm and temperature coefficient equal 2.8 ppm/°C, were obtained, whereas the current noise below 1 nA/√Hz was obtained for lower operating currents. Presented circuit is inexpensive to construct, non-thermally stabilised and very small size (1 × 1.2 in²). The obtained parameters are competitive to commercial current drivers designed for laser applications. The two-stage current source has been successfully implemented in a fully integrated diode-pumped solid-state lasers.

In this study, the authors focus mainly on the investigation of Kriging interpolation method to elaborate surrogate models of the nanoscale double-gate metal oxide silicon field effect transistors (DG MOSFET) analogue/RF performance under critical operational conditions. The elaboration of such models is made possible through the generation of computer experiments using ATLAS-2D simulator, where the numerical simulations or experimental measurements, account for the accurate behaviour of the device including the ageing phenomena, short channel and quantum confinement effects. The validity of the obtained Kriging models is tested by comparing the predicted responses of the device with their numerical counterpart in terms of some statistical criteria namely the sum of relative errors, the mean percentage of absolute errors and the correlation coefficient. It is also shown that the obtained Kriging interpolation models are precise enough to be used as objective functions in the context of a genetic algorithm optimisation with the aim of improving the device analogue/RF performance in terms of transconductance and cut-off frequency parameters. Therefore, this study may provide more insights regarding the investigation of surrogate modelling tools in the field of deep nanoscale devices especially with the intractable mission of developing physical based models at this scale for nanoelectronic simulators.

The main purpose of this research is to investigate a novel implementation method for a surface acoustic wave type (SAWT) electrode-area-weighted (EAW) wavelet inverse-transform processor (WITP). The method of EAW is that the electrode areas of the input and output interdigital transducers (IDTs) are proportional to the envelope areas of the wavelet function (i.e. the two IDTs are identical). By this method, the SAWT EAW WITP is fabricated on X-112°Y LiTaO₃ substrate material. In the study, the diffraction problem and phase difference as two key problems are presented and the solution to two problems are implemented.

This study presents a new realisation of voltage-mode shadow filters based on low-voltage low-power differential difference current conveyor (DDCC). Thanks to the attractive features of the DDCC, including its capability of performing arithmetic operations, the proposed filters offer the advantage of circuit simplicity, minimum number of active and passive elements, and no need for additional summing circuit, compared to the previous available shadow filter designs. The DDCC was designed and fabricated in Cadence platform using 0.35 μm CMOS AMIS process with supply voltage and power consumption of 1 V and 37 µW, respectively. The presented simulation and experimental results using a real chip validate the functionality of the proposed filters.

This study presents a performance comparison of two green electrostatic energy harvesters based on force-sensitive mechanically variable capacitors. A startup battery is required in the conventional electrostatic energy harvester to precharge the mechanically variable capacitor. This adds an extra element to the device and increases the harvester's size and weight. The proposed harvester does not need a startup battery, operates in a regenerative mode, and provides a similar output power. It has a compact size and can start from low voltages. The conventional and regenerative harvesters were developed using mechanically variable capacitors fabricated with renewable materials (i.e. nanocellulose and carbon-coated nanocellulose). The flexible nanocellulose films and the cost-effective fabrication process make the energy harvesters suitable for powering low-power and wearable devices. The bio-based materials further reduce the environmental impact of the devices. Prototypes of the two energy harvesters were built, and their performances were compared on the basis of simulation and measurement results. Both simulation and experimental results are shown to demonstrate the startup and scalable energy availability of the proposed regenerative electrostatic energy harvester for driving low-power devices, such as wireless sensor networks.

Third harmonic current injection technique is one of the best options for harmonic reduction of three-phase controlled/uncontrolled converters. Injecting third harmonics current from dc-bus to the line current reduces its harmonic contents. Minimum THD for any firing angle of controlled converter is function in phase-angle and amplitude of harmonic injection current that can be controlled by single-phase controlled and boost converters, respectively. This scheme is used with three bidirectional switches as harmonic injection device to circulate the injection current to supply currents. This scheme is compared with the state-of-the-art system using zigzag transformer. A novel mathematical analysis for the proposed scheme and state-of-the-art scheme is introduced. The mathematical analysis introduces the optimum values for components on the harmonic injection path at minimum THD and the corresponding efficiency of each scheme. The two schemes under study have been simulated using PSIM program. Two lab prototypes for these two schemes have been implemented. Mathematical, simulation, and experimental results for these two schemes have been introduced, compared, and discussed. The results show the superiority of the proposed scheme.

Traditional overload protection methods usually use either breakers or converters, focused on the side of power supply. However, these schemes may suffer from a slow response time or load dependence. Particularly, the facility may not be able to remain as a regular working condition when an overload occurs. To resolve this problem, the proposed feedback-controlling resonant switching algorithm aims to provide an expected load constant current to protect the load from overload without sacrifice for a normal load operation. On the basis of a negative feedback-control mechanism, the proposed model can detect the load current and thus generate an appropriate switch signal fast and accurately. The switch open period is decided by the model parameters and load current, and it can be set in advance by the timer. On the other hand, the switch closed period is determined by the expected load current that is independent on the load size. The switching acts at the resonant zero-voltage point, so that no power is consumed during the switching action. The performance simulation with DC 28 V supply confirms that the proposed model can maintain a predefined load constant current for an overload protection effectively.

Poor charge transport mechanism and light-induced degradation effects are among the key factors leading to the degraded performance of single-junction amorphous silicon (a-Si:H) solar cells. Existent photovoltaic configurations, based on amorphous silicon carbide (a-SiC:H) window layer, have established efficiencies in the range of 7–10%. Limited performance of such devices has been addressed by replacing a-SiC:H with a wide band gap (∼2 eV) hydrogenated nano-crystalline silicon (nc-Si:H) layer that reportedly exhibits crystalline properties at small scale. Here, the proposed solar cell based on p-nc-Si:H/i-a-Si:H (buffer)/i-a-Si:H/n-a-Si:H configuration has been simulated with SILVACO TCAD by analysing window and intrinsic absorber layers thickness, as well as doping concentrations. Along with the engineering of p/i interface, in-depth evaluation of absorber defects parameters has also been undertaken in order to reduce the recombination rate. The simulated results of an optimised single-junction device demonstrated an open-circuit voltage (VOC) of 0.865 V, short-circuit current density (JSC) of 21.7 mA/cm², Fill factor (FF) of 0.69 and power conversion efficiency of 12.93%, which is promising when compared with the solar cell already reported. The proposed structure will provide the platform for further development of low cost and efficient multijunction thin-film amorphous solar cell technology.

Single-event transients (SETs) due to heavy-ion (HI) strikes adversely affect the electronic circuits in sub-100 nm regime in radiation environment. Time-to-digital converter (TDC) is an important electronic component in many fields such as space applications and is used for measuring time precisely as a digital value. In this study, the effect of SET due to radiation strike on 45 nm vernier-type TDC with a resolution of 7 ps is analysed using cadence spectre circuit simulator. When HI strikes the delay line of TDC close to the START/STOP pulse transition, it either widens or narrows the time interval to be measured, depending on whether it strikes the top/bottom voltage-controlled delay line (VCDL). Results show that the TDC is sensitive if the SET occurs during the transition of START/STOP pulse. Moreover, the change in the time interval occurs in a regular staircase pattern, if the VCDL is struck at all instants near the pulse transition. These errors lead to erroneous digital output and cause abrupt deviations in the staircase transfer characteristics of TDC. SETs in other constituent components of TDC such as D-flip-flop and priority encoder produces glitches which can be mitigated using existing guard gate technique.

In recent times, there is an intense need for a reliable non-invasive diabetes prediction system. Some of the researches in this field suggest that acetone gas in breath has a good correlation to blood glucose levels. Hence, acetone is emerging as a promising bio-marker in diabetes prediction. In this study, acetone levels are measured using quartz crystal microbalance sensor that has wide-scale application as a bio-sensor. It is a piezoelectric sensor which is used to detect and quantify mass variations. The resonant frequency of the sensor changes when there is a deposition of mass on the surface of the crystal. The shift in resonant frequency is directly proportional to the change in the mass concentration. To estimate the performance of this sensor, it is required to understand the sensor's electrical characteristics such as its conductance gain and admittance. This study studies these characteristics and evaluates the behaviour of the sensor in the presence of various acetone concentrations in breath sample for healthy, type 1 and type 2 diabetic subjects.