Optical projection lithography has been the workhorse of the integrate circuit (IC) manufacturing industry to transfer the computer-aided design (CAD) to semiconducting material wafers. The resolution limit of the 193 nm wavelength lithography which was initially targeted for the 90 nm design rule has been further extended to realise ∼10–20 nm devices with ingenious interventions. The three-dimensional fin-shaped field-effect transistor device structure now realise the <20 nm design rule still using 193 nm projection lithography as the widely accepted solution. The extreme ultraviolet wavelength source systems are still in development and testing phases with some recent success reported, but still falling short of supporting volume production requirements. This study reviews the current trends in lithography and the associated resolution enhancement techniques with brief introduction to an integrated CAD analysis for hotspot detection.

This study presents findings of a search on canonic single-resistance-controlled oscillators (SRCOs) using third generation current conveyors (CCIIIs). From seven identified canonic SRCOs, five are completely new. All seven canonic SRCOs use two CCIIIs, two grounded capacitors and three resistors. The condition of oscillation and frequency of oscillations are decoupled and simple. The workability of the presented oscillator configurations have been confirmed by PSPICE simulation and hardware experiments.

A primary-side controlled high-precision constant current AC–DC LED driver, based on source-driving control scheme, is designed for low-power LED-lighting applications in this study. The ratio between demagnetisation time T _Demag and switching period T _S and the primary peak current are remained constant by the proposed control IC, obtaining constant current output. Meanwhile, an adaptive line voltage compensation circuit, integrated in the primary peak current controller, is proposed based on source-driving control scheme. A compensation current proportional to line voltage is injected to the primary-side current sampling pin CS, thus making the turn-off bandgap reference of primary peak current under high-line voltage lower than that under low-line voltage. As a consequence, overshoot phenomena of primary peak current can be avoided, and the line regulation as well as the precision of output current can be improved. The proposed control IC has been fabricated in TSMC 0.35 μm 5 V/650 V CMOS/LDMOS process. Experimental results of a 5 W prototype show that the output current is kept stable at ∼250 mA, and the line regulation is within ±0.5% in a wide range of universal-input ac voltage from 85 to 264 V, and that >80% efficiency is obtained under heavy LED loads.

In this work, a hybrid method-based design of multiplierless two-channel filter bank has been proposed with a given stopband attenuation (A _s) and roll-off factor. Windowing method has been used for efficient design of a prototype filter with novelty of exploiting quantised coefficients in canonical sign digit (CSD) and factorised canonical sign digit (FCSD) space by merging the concept of particle swarm optimisation and artificial bee colony algorithm. The quantised filter coefficients are optimised by varying cut-off frequency such that the magnitude response of prototype filter is approximately reduced to 0.707 at quadrature frequency. The implemented filter is synthesised using target field programmable gate arrays XC3S500E-4-FG320 on Xilinx Spartan 3E starter board. The performances of designed prototype filter is compared with the earlier published works in terms of reconstruction error, amplitude distortion, slices, flip-flops, four-input lookup tables and adders. The synthesis results demonstrate that the significant reduction in hardware is achieved in term of adder gain. For filter order, N = 32, and word length 12, the adder gain achieved in CSD and FCSD is 41.77 and 43.07%, respectively, while for N = 30, it is 35.44% in CSD and 36.70% in FCSD, respectively.

A systematic synthesis approach for floating gyrators employing single z-copy current-controlled current conveyor trans-conductance amplifier (CCCCTA) is presented in this work. Initially, the pathological models of two types of the CCCCTA, namely z-copy z ₊-output CCCCTA (CCCCTA+) and z-copy z ₋-output CCCCTA (z-copy CCCCTA−), are derived by virtue of the nodal admittance matrix (NAM) expansion method. Moreover, these models are then used in the synthesis of floating gyrator using single z-copy CCCCTA. Two floating gyrators are acquired by expanding the NAM of floating gyrator. The synthesised gyrators employ one z-copy CCCCTA and a grounded admittance. Adjusting bias currents of the CCCCTA can tune the parameter of the gyrators. The hand analysis and PSPICE simulation show that the used synthesis method is simple, systematic and valid.

This study presents a new scalable mathematical approach for designing compressors with any arbitrary number of inputs using multi-input threshold gates, behaving as exclusive-OR (XOR). This study relates the theoretical concept to hardware implementation. The methodology is exploited for 3:2, 7:3, and 15:4 compressors, and then implemented by using input capacitors (or resistors) and threshold detectors. The transistor-level realisation of 3:2 and 7:3 compressors is simulated by using Synopsys HSPICE and 32 nm Carbon Nanotube Field Effect Transistors technology. The proposed methodology benefits from the parallel operation of threshold detectors. Therefore, by increasing the number of inputs, the delay parameter does not increase dramatically. The layout views are also provided in order to be able to compare area for the 3:2 compressors with both capacitor and resistor networks.

This study introduces a novel architecture for image steganography using reversible logic based on quantum dot cellular automata (QCA). Feynman gate is used to achieve the reversible encoder and decoder for image steganography. A Nanocommunication circuit for image steganography is shown using proposed encoder/decoder circuit. The proposed QCA circuits have lower quantum cost than traditional designs. It shows the cost effectiveness functionality of the proposed designs. The proposed circuit has 28.33% improvement in terms of area over complementary metal–oxide–semiconductor circuit. To perform image steganography LSB technique is used; signal-to-noise ratio (SNR), peak SNR and mean squared error (MSE) are also computed. The proposed QCA encoder/decoder circuit is suitable for reversible computing. To establish this, the heat energy dissipation by the proposed encoder/decoder circuit is estimated. The estimation shows that the encoder/decoder circuit has very low energy dissipation. Single missing/additional cell-based defect analysis is also explored in this study. Reliability of the circuit is tested against different temperatures. Implementation and testing of the circuit are achieved using QCADesigner tool. MATLAB is used to produce the input to the proposed circuit.

This paper presents a reduced order sliding mode controller based on hysteresis modulation for a boost converter with single voltage multiplier cell (VMC) operating in continuous conduction mode. Although VMC integrated boost converter improves the static gain without extreme duty cycle, it increases the number of components which in turn increases the order of the system. Due to complexity in control of higher order converters, a reduced order sliding mode controller is suggested in this study to reduce the number of sensors. Both static and dynamic performances are improved by considering only two control parameters, the input inductor current and the output capacitor voltage of the VMC integrated boost converter. The robustness of SMC over line variation, load variation and parameter variations are revealed through simulation and compared with conventional PI controller. Inrush current of the VMC integrated boost converter is observed to be high and a startup control with an auxiliary diode is incorporated. A prototype model of a 100 W boost converter with single VMC controlled by SMC is designed and implemented to validate the simulated results. A VMC integrated boost converter with SMC approach offers high voltage gain at reduced duty cycle with improved dynamic characteristics.

This study investigates the performance of the junctionless accumulation-mode (JAM) bulk FinFETs. Different electrical parameters are simulated and analysed for the device with different gate spacer's lengths and materials. Spacers having dielectric constants between 1 and 22 are used to compare the device performance, whereas different spacer lengths are considered in order to understand the effect of spacer engineering. Importance is given to investigate the analogue and radio frequency (RF) performances by computing transconductance (g_m ), transconductance generation factor (g_m /I _d), cut-off frequency (f_T ), maximum frequency of oscillation (f _max) and so on. The device under study shows better ON–OFF current ratio, transconductance, transconductance generation factor using gate spacer having high k-value. However, because of increased gate capacitances, its RF performance degrades with increase in dielectric constant of the spacer used. The effects of downscaling of channel length (L) on analogue performance of the proposed junctionless accumulation mode device have also been presented. It has been observed that the analogue/RF performance of the device can be improved by reducing the spacer length.

Soft errors in semiconductor memories occur due to charged particle strikes on sensitive nodes. Technology and voltage scaling increased dramatically the susceptibility of static random access memories (SRAMs) to soft errors. In this study, the authors present AS8-SRAM, a new asymmetric memory cell that enhances the soft error resilience of SRAMs by increasing the cells critical charge. They run Simulation Program with Integrated Circuit Emphasissimulations and system level experiments to validate the AS8-SRAM cell characteristics at circuit level and evaluate the energy and reliability effectiveness of an AS8-SRAM-based cache memory. The authors’ results show that AS8-SRAM presents up to 58 times less failures in time compared to six-transistor SRAM. Moreover, based on embedded benchmarks experimentations, AS8-SRAM achieves up to 22% reduction in energy-delay product without any considerable loss in performance.

Wireless energy transmission is a key element in Contactless HF Communication Technologies, such as radio frequency identification or near field communication (NFC). This power aspect differentiates the technology from conventional wireless communication. The authors consider the circuit model as a lumped-element description with a coupled-transformer field model to formulate a representation of the problem and include the orientation of the magnetic field in planar space. The authors propose a novel computational model to reveal the dynamics of energy transfer can be represented as a set of forces projected by the oscillator at the interface of free-space. Finally, a high-frequency finite-element simulation based on the authors’ model is used to solve a practical problem of two coupled elliptical spiral-loop antennas of a credit-card size, where the authors consider their contribution in the context of NFC.