A power generation method based fast start-up analysis of resonator based oscillators is presented. The power generation analysis uses a small-signal two-port based approach and is design oriented. The analysis has been validated with detailed circuit level simulations. Several metal–oxide–semiconductor field-effect transistor oscillator architectures have been analysed and the start-up times compared using this analysis.

This paper presents low-power circuits to implement ternary full adder (TFA) using carbon nanotube field-effect transistors (CNTFETs). Besides the unique characteristics of the CNTs, the threshold voltage simple control is the best property to implement ternary logic circuits. Low-complexity, low-power consumption and low-power delay product (PDP) are the benefits of the proposed circuits in comparison with all previous presented designs of TFA. The final proposed TFA is robust and has proper noise margins. The structure of the final proposed TFA is more appropriate to use in ripple adders, since the first ternary half sum generators (THSGs) in all cells produce their outputs in parallel (in the final proposed TFA, the output of the first THSG of the sum-generation unit is also used in the carry-generation unit). The proposed circuits are simulated using HSPICE with 32 nm-CNTFET technology. According to simulation results, the final proposed TFA has reduced the power consumption significantly and results in 86.92 and 97% reductions in terms of the PDP in comparison with two recent proposed designs.

With the recent growth in wireless industry, and changes that occur at a faster pace in radio standards, software defined radio (SDR) provides a flexible solution when compared with hardware radios. Channelisation and sample rate conversion (SRC) are two computational intensive tasks to be carried out in SDR receivers. Reconfigurable anti-aliasing filter and channeliser with minimum reconfiguration overhead is needed for the design of SDR receivers. Low complexity, coefficientless cascaded-integrator-comb filters provides flexible reconfiguration for SRC over a wide integer range, but offers gain droop in the passband of interest. Moreover, they are not suitable for achieving SRC by fractional rates. In this study, the authors propose the design of variable digital filter (VDF) for gain droop compensation and fractional SRC to meet the spectral characteristics of multiple radio communication standards, employing singular value decomposition algorithm. The proposed design of VDF is tested for its reconfigurability with four radio standards, namely, GSM900, WCDMA/CDMA 2000 and WiMAX 802.16. Simulations carried out in MATLAB showed that the proposed VDF had improved spectral response in comparison to other methods proposed in literature.

This study is a step forward to introduce the new fundamentals of LC infinite rectangle circuit network in the fractional domain. The authors first derive the general formula of the impedance between two arbitrary nodes of the fractional-order infinite rectangle circuit network by using Fourier transform in a coordinate system. Then, two properties (relevance and symmetry) of the fractional-order circuit network are systematically discussed. On the basis of these findings, the impedance can also be derived. Moreover, a comparative analysis is carried out to show an excellent agreement between the results obtained here and the results of the previous studies. Furthermore, the effects of the system parameters on the impedance characteristics and phase characteristics are systematically discussed. Finally, four potential application cases are presented. Numerical simulations are presented to verify the theoretical results introduced.

Surface acoustic wave (SAW) delay lines are commonly used devices, and it is important to characterise them to find the causes of deviations between the experimental and theoretical behaviour in order to consider them during design. The authors present the theoretical characteristics and the characterisation of a SAW delay line through X-ray diffraction, energy dispersive X-ray fluorescence, scanning electron microscopy, atomic force microscopy and the measurement of S-parameters. Using the S-parameters, the Y-parameters were calculated and comparing them with those obtained theoretically, they found disagreement in their magnitudes and also that the experimental SAW velocity was 2.8% larger than the theoretical one. The magnitude of experimental Y11 is smaller than that obtained theoretically because of the ill-defined profile and the metallisation ratio of the electrodes is not ideal due to inherent limitations in the fabrication process, and besides Y21 is smaller than expected because the attenuation of the SAW when it propagates through the delay line. When the electrode defects, the experimental SAW velocity and the attenuation coefficient of SAW in this material are considered in the theoretical calculations, agreement is found between theoretical and experimental results. This procedure is based in the comparison between experimental and theoretical Y-parameters and could be used to estimate attenuation, electrode capacitance and SAW velocity.

QR decomposition is extensively adopted in multiple-input–multiple-output orthogonal frequency-division multiplexing wireless communication systems, and is one of the performance bottlenecks in lots of high-performance wireless communication algorithms. To implement low processing latency QR decomposition with hardware, the authors propose a novel iterative look-ahead modified Gram–Schmidt (ILMGS) algorithm based on the traditional modified Gram–Schmidt (MGS) algorithm. They also design the corresponding triangular systolic array (TSA) architecture with the proposed ILMGS algorithm, which only needs n time slots for a n × n real matrix. For reducing the hardware overhead, they modify the TSA architecture into an iterative architecture. They also design a modified iterative architecture to further reduce the hardware overhead. The implementation results show that the normalised processing latency of the modified iterative architecture based on the proposed ILMGS algorithm is 1.36 times lower than the one based on the MGS algorithm. To the best of the authors’ knowledge, the designed architecture achieves the superior latency performance than the existing works.

A bipolar gate drive circuit considering the mitigation of the turn-off losses (E _off) and the overshoot of the collector voltage (V _OV) for the insulated gate bipolar transistor (IGBT) is proposed with 600 V bulk-silicon bipolar-complementary metal–oxide–semiconductor double-diffused metal–oxide–semiconductor technology. Feature of this study is that a differential output circuit and a self-adaptive turn-off gate resistance optimiser are used. By using the differential output circuit, only one power supply is needed to provide the bipolar gate control signal for the driven IGBT. With the proposed optimiser, the turn-off gate resistance can be self-adjusted according to the changing rate of the collector voltage (dV _CE/dt) and collector current (dI _CE/dt) during the turn-off process. Thus, the losses during the dV _CE/dt phase and the dI _CE/dt phase can be designed independently. Due to that the V _OV is only depended on the dI _CE/dt, the authors can reduce the V _OV by 52% without sacrificing the total turn-off losses E _off and a better trade-off can be achieved by using the proposed drive circuit, compared with the conventional one. Numerous formula analysis, simulations and experiments are performed to verify the above electrical characteristics.

This paper presents a phase-error cancellation (PEC) technique that can be employed to achieve fast lock in analogue phase-locked loops (PLLs). The PLL works in fast-lock mode during phase and frequency tracking, and is switched to normal mode after it is almost locked. Unstable system topology is introduced in this system for fast locking. This PEC technique is proposed to cancel the phase error when the output frequency approaches the target value. Due to the inherent oscillation nature of the intentionally designed unstable system in fast-lock mode, the time for PEC can be predicted based on some known parameters. A PLL is simulated in 0.13 µm CMOS process with 1.2 V supply to verify the proposed PEC technique. Simulation results prove that this technique can reduce at least 87% settling time as compared with conventional PLLs.

In this paper, the authors present a polarisation dependent analytical model for DC, radio frequency (RF) and linearity characteristics of a proposed lattice-matched AlInN/AlN/GaN metal–oxide–semiconductor high electron mobility transistor (MOSHEMT). The developed model includes charge controlled analysis derived from triangular potential well approximation along with the spontaneous and piezoelectric polarisation effects. The model accurately predicts the threshold voltage, two-dimensional electron gas sheet charge density, drain current, transconductance and cut-off frequencies for different samples of gate dielectric materials such as SiO₂, HfO₂ and Al₂O₃ over a full range of gate and drain bias. A detailed analysis of the linearity characteristics by investigating the key figure-of-merit metrics such as second-order voltage intercept point, third-order voltage intercept point, third-order input intercept point and third-order intermodulation distortion are performed for different gate dielectric thicknesses of 5, 7 and 10 nm. The accuracy of the model results is verified against Silvaco Technology Computer Aided Design numerical simulation results and found to be satisfactory. It is observed that by careful tuning the device parameters such as dielectric constant and dielectric thickness, lattice-matched AlInN/AlN/GaN MOSHEMT can considerably improve the device performance and suitable for high performance low distortion RF applications.

In this study, design theory and analysis for the class E power amplifier (PA), considering the metal oxide semiconductor field effect transistor (MOSFET) parasitic input and output capacitances, are proposed. The input resistance and capacitances cause non-ideal input voltage at gate terminal, which affect the specifications of the class E PA. In the proposed study, non-linear drain-to-source, linear gate-to-drain and linear gate-to-source MOSFET parasitic capacitances are considered, while zero voltage and zero derivative switching conditions are achieved. Moreover, the input resistance and the value of the input voltage are taken into account in the design theory. According to the obtained results, the duty cycle of the MOSFET depends on the MOSFET threshold voltage, input voltage, input series resistance, and some other parameters, which will be explained in this study. A design example is finally given to describe the design procedure at 1 MHz operating frequency along with the experimental result. The circuit simulation is also performed using PSpice software. The measured results showed quantitative agreements with simulation and theory results.

Asymmetric underlap dual-k spacer hybrid fin field-effect transistor (FinFET) is a novel hybrid device that combines three significant and advanced technologies, i.e. ultra-thin body, three-dimensional (3D) FinFET, and asymmetric spacer engineering on a single silicon on insulator platform. This innovative architecture promises to enhance the device performance as compared with conventional FinFET without increasing the chip area. Recently, high-k dielectric spacer materials are of research interest due to their better electrostatic control and more immune towards short channel effects in nanoscale devices. For the first time, this study introduces an asymmetric high-k dielectric spacer near the source side with optimised length in hybrid FinFET and claims an improvement in device integrity. From extensive 3D device simulation, the authors have determined that the proposed architecture is superior in performance as compared with traditional FinFET.

The authors present a practical design process that considers the power noise problem in CPU blocks for application processors used in smart TVs. The target impedance is determined by modelling the RLC circuit of a system-on-chip power net. The target impedance of a power delivery network is then determined by applying the extracted chip current profile for finalising the design budget. The authors modelled the on-chip power net by combining vector network analyser measurements with an on-chip model for power integrity analysis. The authors demonstrated the optimisation and design strategy by using a ball grid array ball interconnection and case studies on the placement of multilayer ceramic capacitors. The simulation results showed good agreement with the measurement results. The error in the minimum value (negative direction) by voltage droop was less than 8.6%, while the difference in voltage noise ripple was 2.69% for a criterion of 1.1 V assuming a worst-case condition of 1.2 V.