The binary coded decimal (BCD) system is suitable for digital communication, which can be designed by field programmable gate array (FPGA) technology, where look up table (LUT) is one of the major components of FPGA. In this study, the authors proposed a low power and area efficient LUT-based BCD adder which is constructed basically in three steps: First, a new technique is introduced for the BCD addition to obtain the correct BCD digit. Second, a new controller circuit of LUT is presented which is designed to select and send Read/Write voltage to memory cell for performing Read or Write operation. Finally, a compact BCD adder is designed using the proposed LUT. Their proposed 2-input LUT outperforms the existing best one providing 65.8% improvement in terms of area, 44.1% for Read operation and 43.5% for Write operation in power consumption. The proposed BCD adder using FPGA gains a radical achievement compared with the existing best-known LUT-based BCD adder providing prominent better performance of 65.6% in area and 48.3% less power consumption.

A low noise, low power, single-ended to differential switched-capacitor variable gain amplifier (SC-VGA) is designed and fabricated in 0.18 µm complementary metal-oxide-semiconductor technology for a 2–6 MHz second harmonic cardiac ultrasound imaging system. The SC-VGA has 10-bit dB-linear gain steps from −14 to 32 dB which are distributed into two stages, and each stage has a single-stage operational trans-conductance amplifier using floating capacitors to save the power and improve the noise performance. The first stage converts the single-ended input to differential outputs with the 2-bit gain control from 0 to 18 dB, and the second stage exploits 8-bit capacitor arrays to control the gain from −14 to 14 dB. The measured results show that the second harmonic distortion is <−50 dB, the third harmonic distortion is <−50 dB and the integrated noise from 2 to 6 MHz at the output is −64 dBm at the maximum gain and a sampling frequency of 30 MHz. The simulation results match well with the measured results. The SC-VGA works at a supply voltage of 1.6 V and consumes the current of 900 µA. The die size of the SC-VGA is 387 µm × 502 µm.

The synchronous buck converter (SBC) with traditional pulse-width modulation has several disadvantages, such as poor efficiency at light loads. Therefore, this study proposes a new control technique for the SBC that allows power switches to operate with quasi-resonant valley switching in light load conditions. The voltage ripple produced during the capacitor charging and discharging processes is utilised to simulate an inductor current ripple, and thus the zero position of the inductor current can be emulated without requiring a current sensor. The technique has several advantages, including easily built-in integrated circuits. A 5-V/25-W SBC laboratory prototype was implemented to verify the feasibility of the proposed technology and control scheme, and the experimental findings were satisfactory.

In this study, the Class-E/F₃ power amplifier with linear gate-to-drain and nonlinear drain-to-source capacitance is proposed. The analysis for the effect of the parasitic capacitance in the mixed mode Class-E/F₃ with square and sinusoidal gate-to-source voltage has been done. Most of the design equations in this study do not have analytical solutions, and the numerical analyses are used. As can be seen, there is little difference between the results related to the sinusoidal and square gate-to-source voltage. So, only the simulation and experimental result for Class E/F₃ with square gate-to-source voltage at operating frequency of 4 MHz has been done. The results in this study indicate that it is important to consider the effect of the MOSFET gate-to-drain capacitance for achieving the ZVS/ZDS conditions in the Class-E/F₃ power amplifier. The PSpice simulation and measured results are agreed with the analytical expressions, which show the validity of the presented analytical expressions. Finally, the waveforms of Class E/F₃ are compared with equivalent waveforms of Class-E power amplifier, in order to indicate its advantages.

In this study, a design guideline for a modified low-power wideband on-chip amplitude modulator (AM) based on independently driven double-gate metal–oxide–semiconductor field-effect transistor (IDDGMOS) is proposed. The AM performance is then analysed for three different types of underlap engineered IDDGMOS devices. It is observed that the modulator designed with IDDGMOS presents a higher gain and bandwidth for lower power input signals. For analysing the gain–bandwidth performance of the modulator circuit, a small signal model for the devices is considered. The linearity and noise performance of the modulator circuit for different IDDGMOS structures is analysed by studying the 1 dB compression point and the signal-to-noise ratio. The analysis suggested that the most efficient AM circuit performance is achieved for the symmetric underlap IDDGMOS device. The symmetric underlap IDDGMOS AM circuit yields a gain of 11 dB, a bandwidth of 5.5 GHz and a 47.2% efficiency with a distortion less input signal power range of −60 to −33.5 dB. Moreover, the reduced power loss is about 0.047% of the power loss obtained for the conventional complementary metal–oxide–semiconductor device, whereas the bandwidth of the circuit almost triplicates.

This paper proposes two generalised instrumentation amplifier topologies which can operate in voltage, current, transadmittance, and transimpedance mode. Each topology is a two stage structure, wherein an amplifier is used as first stage in the first topology and a converter is employed in the second one. The second stage is difference amplifier for both the structures. The theoretical proposition is verified through operational floating current conveyor (OFCC). The effect of non-idealities of OFCC on system performance, in particular finite transimpedance and tracking error, is also analysed and corresponding mathematical formulation is presented. The functional verification is performed through SPICE simulation using CMOS-based implementation of OFCC. The experimental results using current feedback operational amplifier-based OFCC implementation are also included which are in close agreement with theoretical and simulated results.

This paper presents a low-power complementary metal–oxide–semiconductor (CMOS) clock and data recovery (CDR) integrated circuit (IC) with dynamic voltage scaling (DVS) technique. When DVS is adopted, the power efficiency can be improved by selecting the low supply voltage as possible for a given bit rate. However, the supply voltage generated from a switching regulator such as a buck converter has the ripple voltage at the switching frequency so that the CDR performance may be degraded accordingly. Thus, in this study, the analysis on the relationship among the ripple voltage, the switching frequency and the jitter tolerance (JTOL) is carried out and the appropriate ripple voltage and switching frequency of the buck converter are chosen based on the analysis. Moreover, low supply voltage circuit techniques are carefully utilised for the design of the low-power CDR IC. The CDR IC, implemented in a 0.11 μm CMOS process, shows the power efficiency of 0.97 mW/Gb/s at 4 Gb/s including the buck converter. When 4 Gb/s 2³¹−1 pseudorandom binary sequence is used, the measured bit error rate is better than 10⁻¹², the measured JTOL is 0.3 UI_pp and the measured jitter of the recovered clock is 6.1 ps_rms.

In this study, SPICE models of a multi-antenna system for transmitting and receiving are proposed. The radiation fields at a given direction can be predicted by the transmitting SPICE model when the system is excited by a set of excitation sources. The receiving SPICE model can be used to calculate the coupling voltages on each antenna's load when the antenna system is illuminated by plane waves. The proposed modelling method for transmitting and receiving is a three-step approach. In the first step, the radiation properties of the system are characterized by a minimal number of linearly independent radiation fields. Then, the transmitting and receiving equivalent models are established based on the radiation properties of the system. Finally, the equivalent models are approximated by rational functions and converted to SPICE models. Once these models have been established, the characteristic properties of the excitation signals can be changed arbitrarily without re-establishing the models. Besides, both models can be incorporated with any terminations. The proposed SPICE models have been validated by a commercial full-wave simulator. The feature selective validation method is used to quantify the models' results. Experiments are also conducted to validate the models.

The intellectual property (IP) reuse-based design model is vulnerable to misappropriation and fraud. The situation requires new IP protection mechanisms to guarantee the rights for both IP producers and IP users. In this study, the authors study the constraints used in circuit partitioning and hereby introduce two fingerprinting methods by cell perturbations. They evaluate the proposed methods on ISPD98 benchmark suits by the state-of-the-art partitioner hMetis and cell manipulation. By tuning the fingerprinting strategies, the performance of fingerprinted designs is well maintained. Experimental result shows that the overhead of fingerprinting methods is trivial. The relative Hamming distance of cell fixing method is high, which indicates the method could yield distinct fingerprinting solutions. The relative Hamming distance of cell exchange method is low which is due to the low percentage of cell being fixed.

To qualify as a memristor, the pinched hysteresis loop of a dynamical system corresponding to a sinusoidal excitation signal must be pinched at the origin, for any amplitude, and for any frequency, as well as for any initial condition of the state variable. The above conditions can be checked by the simulations which should be repeated as many times as possible. However, the times of simulation are limited, the finite results drawn through the simulation are not necessarily reliable. To increase the reliability of the judgment, a generalised mathematical model of memristor is designed in the study, which confirms three fingerprints of memristor. HP memristor, piecewise-linear memristor, memristor with square non-linearity and memristor with cubic non-linearity are included as generalised memristor model special cases. The generalised mathematical model of memristor is applied to distinguish memristor from three mathematical model examples. A generalised mathematical model of memristor is a necessary, but not a sufficient condition for judging whether the dynamical system is or not a memristor, which may save us a lot of time and energy.