Online ISSN
1751-8598
Print ISSN
1751-858X
IET Circuits, Devices & Systems
Volume 1, Issue 6, December 2007
Volumes & issues:
Volume 1, Issue 6
December 2007
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- Author(s): A.R. Trivedi ; S. Bandyopadhyay ; M. Cahay
- Source: IET Circuits, Devices & Systems, Volume 1, Issue 6, p. 395 –400
- DOI: 10.1049/iet-cds:20070213
- Type: Article
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p.
395
–400
(6)
The metal-insulator-semiconductor (MIS) and high electron mobility transistor (HEMT) implementations of the spin field effect transistor (SpinFET) proposed by Datta and Das are considered. In both configurations, the SpinFET's switching voltage (for switching on or off) and power dissipation are found to be larger than those of the traditional MISFET or HEMT if the channel length is ≤90 nm. This is a consequence of the fact that spin orbit interaction strengths in semiconductors are too weak to impart any significant advantage to the SpinFET. The issue of non-ideal spin injection and detection at the source and drain contacts is also considered. The SpinFET's on-to-off conductance ratio rapidly degrades with decreasing spin injection/detection efficiency, dropping from infinity (for a one-dimensional channel) to as low as ∼9.5, if the spin injection/detection efficiency drops from 100% to 90%. The transconductance has a quadratic dependence on the spin injection efficiency. These analyses are valid at arbitrary temperatures. - Author(s): T. Mury and V. Fusco
- Source: IET Circuits, Devices & Systems, Volume 1, Issue 6, p. 401 –407
- DOI: 10.1049/iet-cds:20070082
- Type: Article
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p.
401
–407
(7)
Closed-form design equations for the operation of a class-E amplifier for zero switch voltage slope and arbitrary duty cycle are derived. This approach allows an additional degree of freedom in the design of class-E amplifiers which are normally designed for 50% duty ratio. The analysis developed permits the selection of non-unique solutions where amplifier efficiency is theoretically 100% but power output capability is less than that the 50% duty ratio case would permit. To facilitate comparison between 50% (optimal) and non-50% (suboptimal) duty ratio cases, each important amplifier parameter is normalised to its corresponding optimum operation value. It is shown that by choosing a non-50% suboptimal solution, the operating frequency of a class-E amplifier can be extended. In addition, it is shown that by operating the amplifier in the suboptimal regime, other amplifier parameters, for example, transistor output capacitance or peak switch voltage, can be included along with the standard specification criteria of output power, DC supply voltage and operating frequency as additional input design specifications. Suboptimum class-E operation may have potential advantages for monolithic microwave integrated circuit realisation as lower inductance values (lower series resistance, higher self-resonance frequency, less area) may be required when compared with the results obtained for optimal class-E amplifier synthesis. The theoretical analysis conducted here was verified by harmonic balance simulation, with excellent agreement between both methods. - Author(s): A. Italia ; E. Ragonese ; G. Palmisano
- Source: IET Circuits, Devices & Systems, Volume 1, Issue 6, p. 409 –414
- DOI: 10.1049/iet-cds:20070052
- Type: Article
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p.
409
–414
(6)
A design technique to implement a digitally controlled dB-linear variable-gain amplifier (VGA) for high-frequency applications is presented. The design approach is applicable to current-steering VGAs and is based on a digital gain control circuit that operates as a nonlinear digital-to-analogue converter to achieve a digitally controlled dB-linear gain control characteristic. Using the proposed approach, a variable-gain up-converter for 5-GHz wireless LAN applications has been fabricated with a low-cost 46-GHz-fT silicon bipolar technology. The adopted VGA, operating at a frequency of 1 GHz, provides a linear-in-dB gain control characteristic over a 30-dB dynamic range with a 2-dB step and a ±0.8-dB gain error. - Author(s): P.-I. Mak ; S.-P. U ; R.P. Martins
- Source: IET Circuits, Devices & Systems, Volume 1, Issue 6, p. 415 –426
- DOI: 10.1049/iet-cds:20070094
- Type: Article
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p.
415
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(12)
A low-voltage low-power analogue-baseband chain designed for IEEE 802.11a/b/g wireless local-area network (WLAN) receivers is described. It features architecturally a ‘two-step channel selection’ to complement the radio front-end, and a flexible intermediate frequency (IF) reception capability to alleviate the cancellation of frequency and DC-offset. In circuit implementation, a double-quadrature downconverter based on a ‘series-switching’ mixer-quad realises a wideband-accurate I/Q demodulation. A ‘switched-current-resistor’ programmable-gain amplifier (PGA) minimises the bandwidth variation and transient in gain tuning by stabilising, concurrently, the PGA's feedback factor and quiescent-operating point. An ‘inside-OpAmp’ DC-offset canceller creates area-efficiently a very low cut-off frequency high-pass pole at DC while providing a fast settling of DC-offset transients. Fabricated in a 0.35 µm complementary metal-oxide semiconductor (CMOS) process without resorting to any specialised device, the prototype consumes 14 mW per channel at 1 V. The transient time in a 52-dB gain step is <1 µs and the stopband rejection ratio at 20/40 MHz is 32/90 dB. The error vector magnitudes are −27 and −17 dB for 802.11a/g and b modes, respectively. - Author(s): Y.U. Yim ; P.F. Curran ; M. Chu ; J.F. McDonald ; R.P. Kraft
- Source: IET Circuits, Devices & Systems, Volume 1, Issue 6, p. 427 –432
- DOI: 10.1049/iet-cds:20060320
- Type: Article
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p.
427
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(6)
A 52-Gb/s 16∶1 quarter-rate clocking transmitter for high-speed serial data transmission is designed to utilise 0.13-µm SiGe bipolar complementary metal–oxide–semiconductor (BiCMOS) technology. The quarter-rate transmitter consists of a 16∶1 multiplexer (MUX), a voltage-controlled ring oscillator, a phase-locked loop (PLL), a pseudorandom data generator and an output amplifier. The voltage-controlled ring oscillator has a wide tuning range from 11 to 22 GHz with feedforward loop and delay interpolation. A continuous model of a third-order PLL is developed and used to optimise loop filter parameters and to estimate the PLL performance in a simulation. The PLL achieves a low phase noise of −124.6 dBc/Hz at 1 MHz offset. The 16∶1 MUX features quarter-rate clock multiplexing with multi-phase voltage-controlled oscillator clocks. In the design of a 16∶1 MUX, an edge-channelling 4∶1 MUX is used to alleviate a duty cycle and a jitter problem. - Author(s): M.A. Teplechuk and J.I. Sewell
- Source: IET Circuits, Devices & Systems, Volume 1, Issue 6, p. 433 –443
- DOI: 10.1049/iet-cds:20070045
- Type: Article
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p.
433
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(11)
Log-domain circuits offer a low-power property, whereas wave-derived circuits inherit a low-sensitivity property from the ladder prototypes and are less prone to transistor non-idealities. A novel approach to the design of wave filters in the log-domain is presented and several wave two-port topologies are investigated. Important design properties are examined. Realisations of direct filters, complex filters and group-delay equalisers in typical BJT and HBT SiGe BiCMOS technologies are assessed. The design procedures have been incorporated into XFILTER design software. - Author(s): A.P. Vinod ; D. Rajan ; A. Singla
- Source: IET Circuits, Devices & Systems, Volume 1, Issue 6, p. 444 –450
- DOI: 10.1049/iet-cds:20060250
- Type: Article
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p.
444
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(7)
Low-power and high-speed discrete cosine transform (DCT) implementation of the images captured by the satellites presents a hardware design problem. The cost of the DCT implementation is dominated by the complexity of the multiplication of input data (image) with the DCT matrix. The techniques for minimising the complexity of multiplication by employing a differential pixel method are presented. In the proposed method 8×8 blocks of input image matrix are considered, the difference between the adjacent pixels is calculated and those differential pixels are used in DCT transformation. Synthesis results on 0.18 µm CMOS technology show that the proposed method gives an average of 13.2% reduction in power consumption and 10.9% improvement in speed over the conventional method. The proposed method can also be combined with the common subexpression elimination method for further reduction. - Author(s): C.-C. Sun ; S.-J. Ruan ; B. Heyne ; J. Goetze
- Source: IET Circuits, Devices & Systems, Volume 1, Issue 6, p. 453 –461
- DOI: 10.1049/iet-cds:20060289
- Type: Article
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p.
453
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(9)
A computationally efficient and high-quality preserving discrete cosine transform (DCT) architecture is presented. It is obtained by optimising the Loeffler DCT based on the coordinate rotation digital computer (Cordic) algorithm. The computational complexity is reduced significantly from 11 multiply and 29 add operations (Loeffler DCT) to 38 add and 16 shift operations (i.e. similar to the complexity of the binDCT) without losing quality. After synthesising with TSMC 0.13-µm technology library, Synopsys PrimePower was used to estimate the power consumption at gate-level. The experimental results show that the proposed 8-point one-dimensional DCT architecture only consumes 19% of the area and about 16% of the power of the original Loeffler DCT. Moreover, it also retains the good transformation quality of the original Loeffler DCT. In this regard, the proposed Cordic-based Loeffler DCT is very suitable for low-power and high-quality encoder/decoders (codecs) used in battery-based systems. - Author(s): J. Bayard
- Source: IET Circuits, Devices & Systems, Volume 1, Issue 6, p. 462 –469
- DOI: 10.1049/iet-cds:20070088
- Type: Article
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p.
462
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(8)
The transfer function, T, of an ideal integrator is 1/τs. Its phase, equal to −π/2, is independent of the frequency value, whereas the gain decreases in a proportional way with this value of ω. However, on the one hand, it is usually necessary to limit the DC gain so that the transfer function takes the shape T=k/(1+kτs). On the other hand, the active components such as operational amplifiers (op. amps.) or current feedback operational amplifiers are not perfect and they bring a supplementary pole at a high frequency. Therefore the bandwidth where the integrator phase is equal to −π/2 is included between ωMIN and ωMAX. For a couple DC gain and an op. amp. given, increasing the ratio ωMAX/ωMIN to a maximum is proposed. - Author(s): W. Luo ; Z. Zhang ; X. Wang
- Source: IET Circuits, Devices & Systems, Volume 1, Issue 6, p. 470 –476
- DOI: 10.1049/iet-cds:20070057
- Type: Article
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p.
470
–476
(7)
A general design approach to design polymorphic circuits with polymorphic gates is proposed. These polymorphic circuits can adaptively adjust their functionalities with the changes of the electrical characteristics of components induced by the change of environment. The single function circuits that can work correctly and maintain their functionalities in different environments can be regarded as a special kind of polymorphic circuits. The general design approach for these circuits is proposed, and based on this approach, the general design approach to designing polymorphic circuits is also proposed. It is proved that a polymorphic circuit with any two different functions in two different environments can be implemented with a complete polymorphic gate set, and a definition on the gate set is given and the completeness is also discussed. Finally, these general design approaches are analysed and some experiments are performed to demonstrate their efficiency. - Author(s): C.-Y. Lee ; C.W. Chiou ; J.-M. Lin ; C.-C. Chang
- Source: IET Circuits, Devices & Systems, Volume 1, Issue 6, p. 477 –484
- DOI: 10.1049/iet-cds:20060314
- Type: Article
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p.
477
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(8)
A Montgomery's algorithm in GF(2m) based on the Hankel matrix–vector representation is proposed. The hardware architecture obtained from this algorithm indicates low-complexity bit-parallel systolic multipliers with irreducible trinomials. The results reveal that the proposed multiplier saves approximately 36% of space complexity as compared to an existing systolic Montgomery multiplier for trinomials. A scalable and systolic Montgomery multiplier is also developed by applying the block-Hankel matrix–vector representation. The proposed scalable systolic architecture is demonstrated to have significantly less time–area product complexity than existing digit-serial systolic architectures. Furthermore, the proposed architectures have regularity, modularity and local interconnectability, making them highly appropriate for VLSI implementation. - Author(s): M. Zhang ; S.K. Islam ; M.R. Haider
- Source: IET Circuits, Devices & Systems, Volume 1, Issue 6, p. 485 –493
- DOI: 10.1049/iet-cds:20070150
- Type: Article
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p.
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(9)
A programmable frequency divider with close-to-50% output duty-cycle, with a wide division ratio range, is presented. The proposed divider has also provisions for binary division ratio controls, and has demonstrated operation at frequencies as high as 3.5 GHz. With the above features, the proposed divider can be used in phase-locked loops, and is capable of driving various clocked circuits, which need different clock frequencies. The proposed divider has division ratios from 8 to 510, but it can easily be extended to higher ranges by simply adding more divider stages. The divider circuit has been realised in a 0.18-μm RF CMOS process. Test results show that the output duty-cycle is 50% when the division ratio is an even number. For odd division ratios the worst-case duty-cycle is 44.4% when the division ratio is 9. The output duty-cycle becomes closer to 50% when the division ratio is an increasing odd number. For each division ratio, the output duty-cycle remains constant for different chips, with different input frequencies from gigahertz down to kilohertz ranges, and with different power supply voltages. - Author(s): F. Yuan
- Source: IET Circuits, Devices & Systems, Volume 1, Issue 6, p. 494 –508
- DOI: 10.1049/iet-cds:20070103
- Type: Article
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p.
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(15)
A systematic approach for synthesising gyrator-C active transformers using MOS transistors is presented. The topology of gyrator-C active inductors and their characteristics are briefly reviewed first. This is followed by the development of ideal gyrator-C active transformers, where only the capacitor loads of the transconductors synthesising active transformers are considered. The self and mutual inductances of both the primary and secondary windings of active transformers are investigated in detailed. Non-ideal gyrator-C active transformers are developed with the consideration of both the resistance and capacitance loads of transconductors. The intrinsic relation between the self and mutual inductances is derived. The configuration of gyrator-C active transformers with multiple primary and secondary windings is also developed. The proposed active transformers offer large and tunable self and mutual inductances with virtually no silicon area requirement. Several practical implementations of the proposed active transformers have been realised in TSMC-0.18 µm 1.8 V CMOS technology and analysed using SpectreRF with BSIM3v3 device models. Simulation results on voltage transfer characteristics, self and mutual inductances, quality factors, stability, the effect of process variations, and noise are presented. The application of the proposed active transformers is exemplified using a 1.6 GHz active transformer quadrature oscillator. - Author(s): A. Kaltchenko and O. Semenov
- Source: IET Circuits, Devices & Systems, Volume 1, Issue 6, p. 509 –516
- DOI: 10.1049/iet-cds:20070074
- Type: Article
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p.
509
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The increase in process parameter variations and off-state current for deep submicron complementary metal oxide semiconductor (CMOS) technologies makes conventional (single threshold) IDDQ testing ineffective. Delta IDDQ testing performed at two temperatures for a given test vector and called ‘thermal delta IDDQ testing’ is a more attractive alternative and is investigated by the authors. On the basis of statistical Monte Carlo simulations and industrial data, it is shown that lowering the temperature from 330 K to 280 K results in a more than ×100 reduction of IDDQ mean value and approximately ×15 reduction of IDDQ standard deviation of defect-free 0.18 µm CMOS circuits.
Switching voltage, dynamic power dissipation and on-to-off conductance ratio of a spin field effect transistor
Exploring figures of merit associated with the suboptimum operation of class-E power amplifiers
Digitally controlled linear-in-dB variable-gain amplifier for high-frequency applications
Experimental 1-V flexible-IF CMOS analogue-baseband chain for IEEE 802.11a/b/g WLAN receivers
52 Gb/s 16∶1 transmitter in 0.13 µm SiGe BiCMOS technology
Wave realisation of filters and equalisers in log-domain
Differential pixel-based low-power and high-speed implementation of DCT for on-board satellite image processing
Low-power and high-quality Cordic-based Loeffler DCT for signal processing
Propositions to widen the frequency bandwidth of an integrator
Designing polymorphic circuits with polymorphic gates: a general design approach
Scalable and systolic Montgomery multiplier over GF(2m) generated by trinomials
Efficient driving-capability programmable frequency divider with a wide division ratio range
CMOS gyrator-C active transformers
Temperature dependence of IDDQ distribution: application for thermal delta IDDQ testing
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