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Online ISSN 1751-8598 Print ISSN 1751-858X

IET Circuits, Devices & Systems

Volume 1, Issue 2, April 2007

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Volume 1, Issue 2

April 2007

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    • Estimation and control of power electronic device temperature during operation with variable conducting current
      • Author(s): M. Musallam ; P.P. Acarnley ; C.M. Johnson ; L. Pritchard ; V. Pickert
      • Source: IET Circuits, Devices & Systems, Volume 1, Issue 2, p. 111 –116
      • DOI:  10.1049/iet-cds:20060066
      • Type: Article
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      • p. 111 –116 (6)
        Frequent variations in device power loss cause corresponding changes in operating temperature, which may adversely affect device reliability. A method for reducing the device temperature variations is introduced. A simplified third-order thermal model of the device is evaluated in real-time to estimate the instantaneous device temperature. The estimated temperature is used in a temperature control loop to reduce temperature variations by adjusting the device switching frequency. In this way, changes in device conduction loss are counteracted by varying the switching losses, so that the overall losses are substantially constant. The principle is applied to a MOSFET switching a dc load current at random intervals.
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      Empirically-derived capacitor characteristic formulas from distributed modelling
      • Author(s): R.W. Brown
      • Source: IET Circuits, Devices & Systems, Volume 1, Issue 2, p. 117 –125
      • DOI:  10.1049/iet-cds:20060013
      • Type: Article
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      • p. 117 –125 (9)
        Diffusion equation modelling is used to develop formulas for the normally fixed values of capacitance and resistance of the traditional capacitor equivalent circuit. The formulas define the dependence of the equivalent circuit values on metal film resistivity, capacitance per unit area, areal dimensions of the metallisation and on frequency. A multilayer capacitor topology, having both capacitor plates connected at the same end, is used for the derivation, but it is shown that the results are also representative for the more standard double-end connected topologies with some restrictions above the typical self-resonance frequency of these capacitors. The formulas allow accurate prediction of dissipation factor and input impedance according to the design parameters used in constructing the capacitor, thus providing powerful tools in capacitor design. The algorithms also facilitate the determination of internal voltages, currents and power distribution within the capacitor, thus exposing the effects, for example, of partial edge disconnection. The formulas may potentially provide a better capacitor equivalent circuit with dependent variables for circuit emulation. In the paper, the derivation process is described and the formulas tested against experimental results. A simple addition to the equivalent circuit is also included to model dielectric loss which dominantly determines the dissipation factor at low frequency.
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      Characterisation of heat spreader materials for pulsed IGBT operation
      • Author(s): D.J. Lim  and  S.H. Pulko
      • Source: IET Circuits, Devices & Systems, Volume 1, Issue 2, p. 126 –136
      • DOI:  10.1049/iet-cds:20050227
      • Type: Article
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      • p. 126 –136 (11)
        Insulated gate bipolar transistors (IGBTs) have a very high output power and generate correspondingly large amounts of heat. If not dissipated efficiently, this heat will destroy the IC (integrated circuit). Furthermore, since the input to the IGBT is often in the form of a pulsed wave, the rapid repeated heating and cooling of the chip and the surrounding packaging cause physical stresses, which in turn eventually lead to delamination and breakdown. Reducing the magnitude of thermal excursion in pulsed mode operations reduces the amount of stress caused by expansion and contraction, thereby reducing delamination and maintaining component efficiency for a longer period of time. It is therefore important to maintain a low rate of thermal expansion, or have a slow enough change in temperature for the physical stresses not to be damaging. This is normally done with heat sink assemblies, which form an integral part of IGBT design. This study investigates, via simulations using the transmission line matrix method, the thermal responses of some of the popular heat spreader materials. Material combinations within the layered structure of the heat sink assembly will give different thermal responses, and thus an analysis of operational behaviour of these components, with attention given to the input frequency as well as duty cycle, would provide a better guide to designing more suitable and efficient packaging assemblies and heat sinks.
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      Accurate and computer efficient modelling of single event transients in CMOS circuits
      • Author(s): G.I. Wirth ; M.G. Vieira ; F.G. Lima Kastensmidt
      • Source: IET Circuits, Devices & Systems, Volume 1, Issue 2, p. 137 –142
      • DOI:  10.1049/iet-cds:20050210
      • Type: Article
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      • p. 137 –142 (6)
        A new analytical modelling approach to evaluate the impact of single event transients (SETs) on CMOS circuits has been developed. The model allows evaluation of transient pulse amplitude and width (duration) at the logic level, without the need to run circuit level (Spice-like) simulations. The SET mechanism in MOS circuits is normally investigated by Spice-like circuit simulation. The problem is that electrical simulation is time-consuming and must be performed for each different circuit topology, incident particle and track. The availability of a simple model at the logic gate level may greatly improve circuit sensitivity analysis. The electrical response of a circuit to an ionising particle hit depends on many parameters, such as circuit topology, circuit geometry and waveform shape of the charge injection mechanism. The proposed analytical model, which is accurate and computer efficient, captures these transistor-level effects of ionising particle hits and models them to the logic level of abstraction. The key idea is to exploit a model that allows the rapid determination of the sensitivity of any logic gate in a CMOS circuit, without the need to run circuit simulations. The model predicts whether or not a particle hit generates a SET, which may propagate to the next logic gate or memory element, making possible to analyse the sensitivity of each node in a complex circuit. Model derivation is strongly related to circuit electrical behaviour, being consistent with technology scaling. The model is suitable for integration into CAD tools, intending to make automated evaluation of circuit sensitivity to SET possible, as well as automated estimation of soft error rate.
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      Fast and reliable top-level simulation strategy for mixed-signal integrated circuits and its application to DC–DC converters
      • Author(s): H.P. Forghani-Zadeh  and  G.A. Rincón-Mora
      • Source: IET Circuits, Devices & Systems, Volume 1, Issue 2, p. 143 –150
      • DOI:  10.1049/iet-cds:20060241
      • Type: Article
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      • p. 143 –150 (8)
        Top-level, transient, transistor-based simulations are a critical step in the product-development cycle of mixed-signal integrated circuits. These simulations are normally performed just before fabrication and unfortunately impose cumbersome bottlenecks in the design flow. Verification is an iterative process by nature, whereby each problem found requires another simulation to ensure a proper fix is in place, and because of the complexity of a large system, minor errors can cost days, increasing design time and time-to-market. A top-level transistor-based simulation strategy is proposed with minimal time overhead. The strategy is to start with a quick, all macro-model system simulation and gradually substitute one transistor-level sub-block at a time for each additional run. For optimal results, less computationally intensive blocks, which can be determined from a proposed set of screening simulations, are replaced first. The proposed strategy was tested and applied to a buck, current-mode switching regulator, and the results show that simulation overhead is least for linear analogue functions (e.g. op-amps) and worst for high-speed nonlinear circuits (e.g. signal generators). Nonlinear and bi-stable analogue blocks such as bandgap references take more time to simulate than op-amps and less than low frequency digital functions such as power-on-reset, which in turn are less intensive than ramp and pulse generators.
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      Low THD bandpass-based oscillator using multilevel hard limiter
      • Author(s): F. Bahmani  and  E. Sánchez-Sinencio
      • Source: IET Circuits, Devices & Systems, Volume 1, Issue 2, p. 151 –160
      • DOI:  10.1049/iet-cds:20060072
      • Type: Article
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      • p. 151 –160 (10)
        In order to reduce the total harmonic distortion (THD) of a bandpass-based oscillator, instead of using a conventional hard limiter, a multilevel hard limiter (MHL) is proposed which inherently removes the third and the fifth-order harmonics from the frequency spectrum of its output signal. The input–output characteristic of the proposed MHL contains slope values of only zero and infinity, making it easy to implement. The optimal height and width of each stair of the MHL characteristic are derived. Measurement results show that for the same bandpass filter, the proposed approach shows 14 dB improvement in the THD of the output signal with respect to the conventional two-level hard limiter (comparator). The oscillator has been fabricated in TSMC 0.35 µm CMOS process and the die occupies an area of about 3.15 mm2. The oscillator chip prototype operates at the frequency of 10.7 MHz, consumes 40 mA current from a 3.3 V power supply and yields a THD of −53 dB.
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      Design of several asynchronous-logic macrocells for a low-voltage micropower cell library
      • Author(s): K.-S. Chong ; B.-H. Gwee ; J.S. Chang
      • Source: IET Circuits, Devices & Systems, Volume 1, Issue 2, p. 161 –169
      • DOI:  10.1049/iet-cds:20060014
      • Type: Article
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      • p. 161 –169 (9)
        Several asynchronous-logic macrocells for a cell library for low-voltage (1.1 V) power-critical applications are described. The intended application is for the realisation of the datapath of an embedded asynchronous digital signal processor in low-voltage power-critical digital hearing instruments where the speed is relatively low, <5 MHz. The macrocells are two 2-bit and three 16-bit adders, a 16×16-bit truncated parallel multiplier and a 16-bit accumulator. Compared to reported 2-bit adders, one of the 2-bit adders features the lowest energy–delay product (EDP), whereas the other features the lowest energy (power/MHz). Among the three proposed 16-bit adders, two of them feature the lowest EDP compared to the reported designs, and their completion detection circuit is very simple (an OR gate). The truncated parallel 16×16-bit multiplier features the lowest energy multiplier in the literature and this is achieved by truncation and by means of a proposed integrated latch-cum-adder (latch adder) that virtually eliminates the spurious switching in the adder block. The accumulator features the lowest energy accumulator, also by means of the latch adder embodied therein. All macrocells are verified by computer simulations and on the basis of measurements on prototype ICs.
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      Low energy 16-bit Booth leapfrog array multiplier using dynamic adders
      • Author(s): K.-S. Chong ; B.-H. Gwee ; J.-S. Chang
      • Source: IET Circuits, Devices & Systems, Volume 1, Issue 2, p. 170 –174
      • DOI:  10.1049/iet-cds:20060109
      • Type: Article
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      • p. 170 –174 (5)
        The paper presents a low-voltage (1–1.5 V) 16-bit Booth leapfrog array multiplier with emphasis on low energy dissipation, relatively high speed and small IC area. These attributes are achieved in two ways. First, low (hardware) complexity dynamic adders (DAs) are proposed and they are used to reduce spurious switching in the multiplier. Second, the specificities of the leapfrog architecture are exploited with the use of different output rates of the sum and carry outputs of the proposed DAs. When compared with other array multiplier designs, the proposed multiplier features the lowest energy dissipation and one of the shortest delays, resulting in the lowest energy–delay product. Furthermore, when compared with the reported dynamic array multiplier that features somewhat similar electrical characteristics, the proposed multiplier is advantageous in its substantially smaller (∼33%) IC area. Based on a 0.35 µm dual-poly four-metal CMOS process and at 1 V operation, the proposed multiplier dissipates ∼18 pJ, has a delay of ∼188 ns and occupies 0.11 mm2 of IC area. The proposed design is appropriate for low-voltage energy-critical and IC area-critical applications including hearing aids.
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      Design of efficient multiplierless FIR filters
      • Author(s): D.L. Maskell
      • Source: IET Circuits, Devices & Systems, Volume 1, Issue 2, p. 175 –180
      • DOI:  10.1049/iet-cds:20060201
      • Type: Article
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      • p. 175 –180 (6)
        An algorithm for reducing the hardware complexity of linear phase finite impulse response digital filters that minimise the adder depth in the multiplier block adders (MBAs) is presented. The algorithm starts by aggressively reducing both the coefficient wordlength and the number of non-zero bits in the filter coefficients. This reduces the number of adders (the adder depth) that are needed to construct the coefficient multiplier and results in an increased operating frequency. A modification to the representation of the filter coefficients such that the number of full adders (FAs) in our hardware implementation is proportional to the product of the input signal wordlength and the number of adders is proposed. That is, in general, the number of FAs is independent of the coefficient wordlength and the number of shifts between non-zero bits in the coefficient. Results show that the proposed technique achieves a 67 and 70% reduction in the number of MBAs and the number of multiplier block FAs, respectively. A software program has been implemented, which generates a Verilog HDL description of the digital filter. The proposed technique is not limited to filters with only a small number of taps and has been successfully applied to filters with up to 500 taps.
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      Fastest linearly independent arithmetic transforms and their calculation on systolic array processors
      • Author(s): C.C. Lozano  and  B.J. Falkowski
      • Source: IET Circuits, Devices & Systems, Volume 1, Issue 2, p. 181 –192
      • DOI:  10.1049/iet-cds:20060263
      • Type: Article
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      • p. 181 –192 (12)
        Fastest linearly independent arithmetic (LIA) transforms have computational costs that are lower than that of the standard arithmetic transform. They also possess fast direct and inverse transforms that enable their efficient calculation using fast transform and make them suitable for systolic array implementation. Calculation of fastest LIA transform spectral coefficients by systolic array processor is described here. New fastest LIA transforms are introduced and various properties that are relevant to the fastest LIA transform spectra calculation are presented. General steps for deriving the linear systolic array structures are listed and examples are given for several previous and new fastest LIA transforms. It is shown that the number of linear systolic array structures required for obtaining the best fastest LIA transform is smaller than the number of all possible fastest LIA transforms. Experimental results for the fastest LIA transforms are also shown and compared with the standard arithmetic transform. The comparison shows that the fastest LIA transforms have smaller numbers of non-zero spectral coefficients for many binary functions.
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