Online ISSN
1751-8598
Print ISSN
1751-858X
IET Circuits, Devices & Systems
Volume 1, Issue 1, February 2007
Volumes & issues:
Volume 1, Issue 1
February 2007
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- Author(s): S. Marsh ; B. Alderman ; D. Matheson ; P. de Maagt
- Source: IET Circuits, Devices & Systems, Volume 1, Issue 1, p. 1 –6
- DOI: 10.1049/iet-cds:20060212
- Type: Article
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Techniques are presented for designing fixed-tuned millimetre-wave components with the least number of parts to minimise the cost and maximise the potential for volume manufacture. Design techniques for millimeter-wave mixer components targeted at potentially high volume applications, such as medical and security screening and nondestructive testing, require certain compromises in the use of CAD tools. The compromise techniques are demonstrated using commercially available foundry diodes in the design of a 183 GHz subharmonic mixer for earth observation applications. The resulting mixer exhibits 6.85 dB double sideband conversion loss and a mixer temperature of 988 K using 5 mW of local oscillator power at 92 GHz. - Author(s): H. Alzaher ; M. Al-Ghamdi ; M. Ismail
- Source: IET Circuits, Devices & Systems, Volume 1, Issue 1, p. 7 –12
- DOI: 10.1049/iet-cds:20050355
- Type: Article
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7
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Design of a CMOS 18th-order IF (intermediate frequency) bandpass filter for integrated low-IF Bluetooth receivers is presented. The centre frequency and bandwidth of the filter are 3 and 1 MHz, respectively. The proposed filter is based on unity gain fully differential voltage buffers and provides efficient, low power and a small area design solution. The filter, including its automatic tuning circuit, occupies an area of 0.6 mm2 in a standard 0.5 µm-CMOS chip. Experimental results show that the filter satisfies the selectivity and dynamic range requirements of Bluetooth while operating from a total supply current of 0.9 mA. - Author(s): A.P. Vinod ; A. Singla ; C.H. Chang
- Source: IET Circuits, Devices & Systems, Volume 1, Issue 1, p. 13 –20
- DOI: 10.1049/iet-cds:20050324
- Type: Article
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A minimal-difference differential coefficients method is presented for low power and high-speed realisation of differential-coefficients-based finite impulse response filters. The conventional differential coefficients method (DCM) uses the difference between adjacent coefficients whereas we identify the coefficients that have the least difference between their magnitude values and use these minimal difference values to encode the differential coefficients. Our minimal-difference differential coefficients can be coded using fewer bits, which in turn reduces the number of full additions required for coefficient multiplication. By employing a differential-coefficient partitioning algorithm and a pseudofloating-point representation, we show that the number of full adders and the net memory needed to implement the coefficient multipliers can be significantly reduced. The proposed method is combined with common subexpression elimination for further reduction of complexity. Experimental results show the average reductions of full adder, memory and energy dissipated achieved by our method over the DCM are 40, 35 and 50%, respectively. - Author(s): T. Johnson ; R. Sobot ; S. Stapleton
- Source: IET Circuits, Devices & Systems, Volume 1, Issue 1, p. 21 –26
- DOI: 10.1049/iet-cds:20060054
- Type: Article
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An analysis of a continuous-time bandpass sigma–delta modulator in a configuration with an upconverter is given for a RF class D amplifier application. The upconverter multiplies the modulator pulse train with a synchronised clock signal and maps each modulator bit to an integer multiple k of a (+1, −1) or (−1, +1) pattern depending on the sign of the modulator bit. The upconversion is equivalent to an extension of Manchester encoding, which is usually defined for k=1. The analysis focuses on evaluating the impact of upconversion on the modulator coding efficiency and the average pulse period. A design equation is derived, which shows that coding efficiency is dependent only on the upconversion frequency ratio, while the average pulse period depends only on k. The equations provide a designer with a way of evaluating the trade-offs in the amplifier system and show that encoding with k=1 is the most efficient configuration for maximising coding efficiency and minimising switching power loss. - Author(s): J.-R. Guo ; C. You ; M. Chu ; P.F. Curran ; J. Diao ; B. Goda ; P. Jin ; R.P. Kraft ; J.F. McDonald
- Source: IET Circuits, Devices & Systems, Volume 1, Issue 1, p. 27 –33
- DOI: 10.1049/iet-cds:20050065
- Type: Article
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Implementation of a silicon germanium (SiGe) field programmable gate array (FPGA) has been described. The reconfigurable basic cell (BC) that evolved from the Xilinx XC6200 has been redesigned to achieve high speed with lower power consumption. The propagation delay of the BC in comparison to the BC implemented in the earlier generation SiGe process has been reduced to 18% of its original value (from 240 to 42 ps) and the power consumption has been comparably reduced. The range of power reduction is from 13% of its original value when the BC is fully turned on down to 2% when the power saving scheme is applied. A 20×20 SiGe FPGA with physical dimensions of 4.5×4.8 mm has been fabricated using the IBM 120 GHz (7HP) process. To deliver a 10 GHz clock, an H tree has been designed and implemented with reduced skew. To demonstrate its performance, a 4∶1 multiplexer (MUX) has been mapped for comparison with various CMOS FPGAs. The SiGe FPGA can achieve an 8 Gbps transmission rate, which is a 40 times improvement over the same implementation on a Xilinx Virtex CMOS FPGA. Other comparisons between the SiGe FPGA and commercial FPGAs have also been included. From simulations and measurements, the SiGe FPGAs have been shown to have high performance that can successfully tackle gigahertz applications. - Author(s): I.S. Stievano ; I.A. Maio ; F.G. Canavero
- Source: IET Circuits, Devices & Systems, Volume 1, Issue 1, p. 34 –40
- DOI: 10.1049/iet-cds:20045152
- Type: Article
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The development of macromodels of differential drivers for the prediction of the analogue operation of very high-speed digital communication links is explored. The macromodels are mathematical relations hiding the information on the internal structure of devices; they are estimated from port device responses and can be easily implemented in any circuit or analogue mixed-signal simulator as SPICE-like subcircuits or VHDL-AMS code descriptions. Accuracy and efficiency are assessed by applying the modelling procedure to actual devices. - Author(s): C. Bronskowski and D. Schroeder
- Source: IET Circuits, Devices & Systems, Volume 1, Issue 1, p. 41 –48
- DOI: 10.1049/iet-cds:20060182
- Type: Article
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A methodology for the systematic design of a programmable operational amplifier (opamp) is described. With this methodology, the opamp is programmable concerning noise and power consumption while keeping the stability for the whole operation range with a constant phase margin of ϕres=70°. The theoretical model is developed with the help of the transfer characteristics of the opamp determining the degrees of freedom. Experimental results for a 0.35-µm CMOS opamp show either ultra low-noise of 2 nV/√Hz or low-power consumption of 140 µW while keeping the opamp stable over the whole range of programmability. - Author(s): R. Haque ; K. Tedrow ; B. Srinivasan
- Source: IET Circuits, Devices & Systems, Volume 1, Issue 1, p. 49 –56
- DOI: 10.1049/iet-cds:20060032
- Type: Article
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The design of a flash-based reference voltage generator used to generate the drain bias reference voltage for flash sensing is described. The flash cell drain must maintain a stable voltage during read operation, irrespective of supply voltage within the chip, to avoid drain disturb condition. Since this reference voltage needs to supply the entire chip, the high capacitance associated with this node usually requires a long time to power-up. A scheme used to reduce the power-up time by a factor 20× from conventional design, while maintaining the design required precision of 2% in the reference voltage output is described. Since the circuit is also required to be ON during the entire operational phase of the chip, design methods used to lower the current consumed by the circuit using a sample-and-hold scheme are also discussed. - Author(s): K.-H. Chen ; C.-C. Chien ; C.-H. Hsu ; L.-R. Huang
- Source: IET Circuits, Devices & Systems, Volume 1, Issue 1, p. 57 –62
- DOI: 10.1049/iet-cds:20050331
- Type: Article
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57
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An optimum power metal-oxide-semiconductor field effect transistor (MOSFET) width technique is proposed for enhancing the efficiency characteristics of switching DC–DC converters. By implementing a one-cycle buck DC–DC converter, it is demonstrated that the dynamic power MOSFET width controlling technique has a much improved power reduction whether the load current is light or heavy. The maximum efficiency of the buck converter is ∼92% with a 3% efficiency improvement for the heavy load condition. The efficiency is further improved by ∼16% for the light load condition as a result of the power reduction from the large power MOSFET transistors. Also proposed is a new error-correction loop circuit to enable a better load regulation than that of previous designs. Compared with the adaptive gate driver voltage technique, the optimum power MOSFET width can achieve a significant improvement in power saving. It is also superior to the low-voltage-swing MOSFET gate drive technique for switching DC–DC converters. - Author(s): P.S. Crovetti and F. Fiori
- Source: IET Circuits, Devices & Systems, Volume 1, Issue 1, p. 63 –71
- DOI: 10.1049/iet-cds:20050373
- Type: Article
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A compact, very low voltage, temperature-independent reference circuit, which is based on the thermal properties of bipolar junction transistors in the saturation region is presented. The new circuit operates from a minimum power supply of less than 1V and provides a reference voltage with a nominal thermal drift of ∼30 ppm/°C in the temperature range between −40 and 110°C. The proposed circuit has been integrated on silicon by a 0.35 µm CMOS technology and a reference voltage with a measured untrimmed thermal drift of ∼100 ppm/°C has been reported. The new voltage reference occupies a silicon area of only 3,500 µm2, shows a power consumption of <30 µW and its DC power supply rejection is better than 65 dB. - Author(s): S. Maheshwari
- Source: IET Circuits, Devices & Systems, Volume 1, Issue 1, p. 72 –78
- DOI: 10.1049/iet-cds:20060196
- Type: Article
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Three new circuit topologies for first-order all-pass filters, each with two variations, realising six new first-order voltage-mode all-pass sections are proposed. Each circuit employs two differential voltage current conveyors and three grounded passive components, ideal for IC implementation. All the circuits possess high input impedance, which is a desirable feature for voltage-mode circuits. As an application, a new quadrature oscillator circuit is realised using one of the proposed all-pass circuits. PSPICE simulations using 0.5 µm CMOS parameters confirm the validity and practical utility of the proposed circuits. - Author(s): J.G.R.C. Gomes ; A. Petraglia ; S.K. Mitra
- Source: IET Circuits, Devices & Systems, Volume 1, Issue 1, p. 79 –86
- DOI: 10.1049/iet-cds:20050315
- Type: Article
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The authors previously considered the application of multilayer perceptrons (MLPs) to block coding at the sensor level of modern imaging systems, and have proposed analogue encoders with transistor-count complexity that is low enough to suit focal-plane implementation. In the paper, they extend the on-sensor block coding MLP study, to include a statistical analysis of the MLP sensitivity to implementation errors occuring in standard CMOS fabrication processes. Employing simple offset models, a comparison is made of the MLP with other block encoders based on full-search entropy-constrained vector quantisation (ECVQ) of the data, and it is verified that the MLPs are less sensitive over a wide range of rate-distortion compression points. By introducing a realistic linear model that takes into account sensitivity and the complexity performances for both systems, the authors verify that, for MLPs, the sensitivity becomes less dependent on the complexity as the expected quality loss is allowed to increase. Without setting a limit on the expected quality loss, the MLPs are consistently better than the ECVQs, both in terms of sensitivity and complexity for a precision equivalent to 6 bits. - Author(s): F. Taghibakhsh and K.S. Karim
- Source: IET Circuits, Devices & Systems, Volume 1, Issue 1, p. 87 –92
- DOI: 10.1049/iet-cds:20060217
- Type: Article
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On-pixel amplifiers in amorphous silicon (a-Si) technology are an attractive replacement for industry standard on-pixel switch architectures in active matrix flat panel imagers in order to meet the low noise requirements of low-dose digital imaging modalities such as x-ray fluoroscopy and, more recently, 3D mammography tomosynthesis. However, implementing a-Si pixel amplifiers requires high-performance thin film transistors (TFTs) that are relatively large in size. In this research, a novel high dynamic range amplified pixel architecture using only two TFTs is introduced that is capable of amplifying the sensor value with a user controllable gain over a wide input range. Circuit operation and driving circuits required for on-pixel amplifier arrays are investigated, and simulation results are presented that indicate the feasibility of this pixel architecture for high resolution, low noise and x-ray tomosynthesis applications. - Author(s): S.-J. Jou ; C.-H. Lin ; Y.-H. Chen ; Z.-H. Li
- Source: IET Circuits, Devices & Systems, Volume 1, Issue 1, p. 93 –101
- DOI: 10.1049/iet-cds:20045173
- Type: Article
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A performance evaluation and circuit architecture for all-digital data recovery using an oversampling method is proposed. The architecture is very regular and hence very suitable for standard-cell implementation flow. Due to its feedforward architecture, the required bit-rate can be achieved through proper pipelining. These properties make the proposed architecture very suitable as soft silicon intellectual property. Analysis of BER due to the combined effects of the key design parameters like data jitter, clock jitter and oversampling ratio in the oversampling technique are carried out. Thus different specifications of data recovery can be designed with different design parameters. A module generator that can estimate the design parameters automatically is established. Design implementation shows the proposed all-digital data recovery circuit can achieve 3.07 Gbit/s (post-layout) with 0.25 µm 2.5 V CMOS technology standard-cell design and occupies 380×390 µm2 chip area. - Author(s): G. Jaberipur and B. Parhami
- Source: IET Circuits, Devices & Systems, Volume 1, Issue 1, p. 102 –110
- DOI: 10.1049/iet-cds:20050228
- Type: Article
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Redundant representations play an important role in high-speed computer arithmetic. One key reason is that such representations support carry-free addition, that is, addition in a small, constant time, independent of operand widths. The implications of stored-transfer representation of digit sets and the associated addition schemes, as an extension of the stored-carry concept to redundant number systems, on the speed and cost of arithmetic algorithms, are explored. Two's-complement digits as the main part and any two-valued digit (twit) in place of a stored carry are allowed, leading to further broadening of the generalised signed-digit representations. The characteristics of the digit sets, possibly not having zero as a member, that allow for most efficient carry-free addition, are investigated. Circuit speed is gained from storing or saving, instead of combining through addition, the interdigit transfers generated during the carry-free addition process. Encoding efficiency is gained from using a twit-transfer set encoded by one logical bit, where more bits would otherwise be needed to represent a transfer value.
Design of low-cost 183 GHz subharmonic mixers for commercial applications
CMOS low-power bandpass IF filter for Bluetooth
Low-power differential coefficients-based FIR filters using hardware-optimised multipliers
Manchester encoded bandpass sigma–delta modulation for RF class D amplifiers
Silicon germanium programmable circuits for gigahertz applications
Macromodelling of differential drivers
Systematic design of programmable operational amplifiers with noise–power trade-off
Design of a flash-based reference voltage generator for drain bias circuit
Optimum power-saving method for power MOSFET width of DC–DC converters
Compact, very low voltage, temperature-independent reference circuit
High input impedance VM-APSs with grounded passive elements
Sensitivity analysis of multilayer perceptrons applied to focal-plane image compression
High dynamic range 2-TFT amplified pixel sensor architecture for digital mammography tomosynthesis
Design and analysis of digital data recovery circuits using oversampling
Stored-transfer representations with weighted digit-set encodings for ultrahigh-speed arithmetic
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