Continuous health monitoring for an infant is crucial for detecting and preventing several diseases. Recent advancement in wearable technology has given rise to the development of wearable infant health monitoring systems (WIHMSs). These systems provide an edge over conventional infant health monitoring systems which are not only bulky and uncomfortable for the infants but are also limited to the clinical settings. This study reviews some state-of-the-art WIHMS, mentions the advantages, limitations and the challenges faced by such systems. This study, for the first time, contributes an appraisal of research prototypes and commercially available systems for WIHMS, which is the need of the day.

In this study, a model-order reduction approach based on approximate Gramians for second-order time-delay systems is proposed. By treating the second-order time-delay system as a special case of the integro-differential system, it exhibits a connection with the time-delay Gramians of the corresponding first-order system. After applying the approximate Gramians and balanced truncation procedures, the resulting reduced system is expected to well approximate the original system. Besides, the -embedding technique is applied to the case when the damping matrix of the second-order time-delay system is singular. Finally, numerical examples show the good performance in the time domain and the finite frequency range.

In this study, the authors have proposed a Write Assist Low Power 11T (WALP11T) SRAM cell. To analyse its performance in terms of major design metrics, the proposed cell has been compared with contemporary SRAMs like the Fully Differential 8T (FD8T), Single-Ended Disturb Free 9T (SEDF9T), Bit-interleaving architecture supporting 11T (BI11T), Self-refreshing Logic-based 12T (WWL12T) and Differential 12T (D12T) cells. The proposed cell exhibits significantly shorter read/write delay when compared to most comparison cells. It shows considerably higher read stability and write ability than that of FD8T and SEDF9T/D12T/WWL12T, respectively. Moreover, WALP11T dissipates significantly lower leakage power in comparison to the majority of comparison cells and exhibits 2.21 × /1.18 × lower read power delay product (R _PDP) than that of BI11T/D12T and 5.12 × /1.39 × /1.09 × lower write power delay product (W _PDP) than that of BI11T/WWL12T/D12T. The proposed cell consumes considerably lower area than WWL12T/D12T and shows highly reliable operation when subjected to the harsh process, voltage and temperature variations at both Slow NMOS-Fast PMOS and Fast NMOS-Slow PMOS corners. For all these improvements, WALP11T shows longer read/write delay than FD8T, higher leakage power and power delay product than BI11T and FD8T/SEDF9T, respectively, at V _DD = 0.3 V.

This study presents the optimisation of the various parameters (wt% of multiwalled carbon nanotube, pore size, size of the middle plate and time of testing) for evaluation of fractional exponent of a solid-state fractional capacitor. For this, full factorial design of experiments is carried out to understand the crucial parameters, which have an effect on fractional exponent . Then, contributions of each of the significant parameters are estimated. Later, by one-way analysis of variance, the combination of various parameters by which one can obtain fractional capacitors of varying is given in detail. The fractional capacitor for which the optimised design is done has a constant phase angle in between 0° and −90° in the frequency range from 1 to 100 kHz.

In this work, a digital phase-locked loop (DPLL) is proposed for the low power and stable operation in an augmented reality (AR) display system. The AR display system which needs the ultra-low power consumption adopts the near-threshold voltage (NTV) operation in both digital and analogue blocks. The NTV region has the advantage of small power dissipation with low-supply voltage. However, it suffers from performance degradation due to a large delay, slow transition time, and small dynamic voltage range. To achieve the optimised power efficiency and stable performance, the dynamic time-to-digital converter and the low voltage optimised digitally controlled oscillator are applied in the proposed DPLL. In addition, the forward body biasing scheme is used to increase the operation frequency for the sigma-delta modulator block. The proposed DPLL is fabricated using 65 nm CMOS technology and shows a current consumption of 160 μA at a voltage of 0.55 V. In addition, the jitter characteristic shows 6.7 ps rms jitter and 50 ps peak to peak jitter at 480 MHz.