To the best of the author's knowledge, several studies during 1960–2019 were carried out on wideband and ultrawideband LNAs just to render optimum LNAs for SAW‐less Radio‐Frequency Integrated Circuits (RFICs) but none of these works reviewed and taught the proceedings of these six decades, hence the lack of a comprehensive review is quite noticeable. This article specifically studies the challenges and solutions of designing UWB LNA by reviewing topologies and techniques such as inductive peaking, noise and distortion cancellation, g _m ‐boosting, active inductor and notch filter. Its historical aspect illustrates when the idea of wideband LNA was born and how it changed to ultrawideband LNA, and its tutorial aspect discusses circuits and achievements to present optimum LNAs in Complementary MOS (CMOS), BiCMOS and High‐Electron‐Mobility Transistor (HEMT) technologies. This work describes the endeavours of engineers in reaching UWB LNA from narrowband LNA during six decades that have great importance as a chapter in understanding this topic because it teaches all topologies, techniques, circuits and related events in a historical narrative for trained readers who are not experts on this topic.

This study presents a numerical analysis to correlate performance characteristics of indoor photovoltaic (PV) devices with those of DC‐to‐DC up‐converters designed for low‐power electronic applications. A theoretical model based on self‐consistent solution of Poisson's equation and continuity equation under optical generation‐recombination conditions has been applied to design Cu₂ZnSn(SSe)₄‐based PV devices having type‐I and type‐II energy band profiles, such that they can operate with peak efficiencies of 12.6% and 14.1%, respectively, under illumination from an experimentally characterized white light‐emitting diode. Each PV device has been subsequently utilized as the input source of a Meissner oscillator‐based self‐driven DC‐to‐DC converter. Comparative analysis shows that in spite of the lower PV conversion efficiency, the PV device having higher short‐circuit current density results in a higher output efficiency of the converter circuit. Similar characteristic trends are obtained for a boost converter operating in a discontinuous conduction mode, whereas a continuous conduction mode of operation results in the opposite trend. The underlying reason behind such an observation has been traced back to the transient behaviour of the inductor current of the converter. The results of this study suggest close correlation between physics‐based design parameters of the PV device and output performance characteristics of the converter circuit.

Digital‐to‐analogue converters (DACs) are essential blocks for interfacing the digital environment with the real world. A novel architecture, using a digital‐to‐time converter (DTC) and a time‐to‐voltage converter (TVC), is employed to form a low‐power time‐based DAC (T‐DAC) that fits low‐power low‐speed applications. This novel conversion mixes the digital input code into a digital pulse width modulated (D‐PWM) signal through the DTC circuit, then converts this D‐PWM signal into an analogue voltage through the TVC circuit. This new T‐DAC is not only an energy‐efficient design but also an area‐efficient implementation. Power optimization is achieved by controlling the supply voltage of the TVC circuit with a discontinuous waveform using a low bias current. Moreover, the implementation area is optimized by proposing a new DAC architecture with a coarse‐fine DTC circuit. Post‐layout simulations of the proposed T‐DAC is conducted using industrial hardware‐calibrated 0.13 μm. Complementary metal oxide semiconductor technology with a 1 V supply voltage, 1 MS/s conversion rate, and 0.9 μW power dissipation.

The incorporation of Si_1−x Ge _x nanowire based metal‐semiconductor‐metal (MSM) Schottky biristor allows the conceptualization and realization of low latch‐up and latch‐down voltages with retained latching window. With the aim of investigating the device governing physics and device performance, mathematical simulation is carried out using exhaustive and calibrated 2D Technology computer‐aided design (TCAD) device simulation. The device performance is investigated with respect to channel doping, electrode work function, channel length, temperature and mole fraction (x) to maximize the latching window size and minimize the latch‐up voltage. The detailed sensitivity analysis is also carried for the proposed device with parametric sweep method.

A scheme to implement the Jerk form of the Chua system family using a controllable canonical form applied in linear systems is proposed. The main thought is that the nonlinear function with a single independent variable input can be superposed by a multiple linear function, which is regarded as the input of the system, and its single variable is regarded as the output of the system. Its state space could be reconstructed into the controllable canonical form. The output after transformation is fed back to the nonlinear function as its input independent variable, thus the controllable canonical form is transformed into the Jerk form of the Chua’s chaotic system. All Jerk forms of three‐order Chua system, and part Jerk forms of four‐order Chua system are presented. Analysis of the Lyapunov exponent spectrum, eigenvalues of the original three‐order, four‐order Chua systems and their Jerk forms, and the same values demonstrate the equivalent of the systems for both structures. According to the complexity and National Institute of Standards and Technology (NIST) test results, the pseudo‐random performance of the chaotic sequence brought by the Jerk forms of the Chua system is better. The simplest unified circuit block diagram for the Jerk forms of the Chua’s family is also given. By changing their resistance parameters, the bifurcation diagrams show that Jerk forms’ systems are entering chaos, these circuits implement results of 2–6 scroll attractors. Experimental observations are provided for confirmation.