A new differential substrate integrated waveguide (SIW) antenna with good common-mode (CM) suppression and high gain is presented. The designed antenna uses an H-shaped slot backed by SIW cavity and is differentially excited by two microstrip feedlines from two opposite sides of the cavity. The measured differential impedance bandwidth of the proposed antenna is 10.19–11.03 GHz with CM suppression below 2 dB. The designed differential antenna exhibits a high gain of 8.7 dBi with a good front-to-back ratio of 21 dB.

A novel low-profile single-fed circularly polarised single-layer metasurface antenna for wideband operation is proposed in this Letter. The metasurface antenna consists of nine unit cells arranged in a 3 × 3 layout. Four slits are incorporated into four of them, respectively, to form two orthogonal currents with 90° phase difference; hence, circularly polarised fields are excited. Moreover, a modified L-type slot is etched on the middle lattice to improve impedance bandwidth and axial ratio performance. The proposed dielectric-filled (ɛ _r = 3.5, tan δ = 0.001) antenna with a low profile of 0.038λ ₀ (λ ₀ is the working wavelength at 5.7 GHz in free space) achieves about 18.0% measured −10 dB impedance bandwidth. The measured 3-dB axial ratio bandwidth of the proposed antenna is about 12.8% (5.35–6.08 GHz) with a broadside gain of more than 6.9 dBi.

A novel design for a simple and compact monopulse feed is presented for illuminating a deep reflector from the primary focal point, e.g. a rotationally symmetric single-reflector parabolic antenna, with a diameter-to-focal-distance ratio of around 0.4. The proposed feed is designed as a multimode circular cavity (cup) antenna. The elliptical patch excites a left-hand-circularly polarised mode for the sum channel. The monopole in the centre of the patch excites the orthogonal, linearly polarised mode for the difference channel. Two prototypes for such a feed were developed and fabricated, where the first was a proof-of-concept device and the second was a computer simulation-optimised version. Both the simulations and the measurements of the optimised prototype are presented.

A novel 0-2 Multi-Stage Noise Shaping (MASH) analogue-to-digital converter (ADC) is proposed. The first stage is implemented using a 4-bit SAR ADC. The second stage uses a voltage controlled oscillator (VCO)-based quantiser (VCOQ). Unlike earlier VCOQs which provide first-order noise shaping, the VCOQ proposed in this Letter achieves second-order noise filtering. To implement this noise shaping, the quantisation noise of the VCOQ is extracted as a pulse-width-modulated signal, and it is fed back to the VCO input using a charge pump circuit. In the proposed scheme, the input signal to the VCO is small. Therefore, the linearity requirement of this block is relaxed. Also, any error related to the charge pump circuitry will be first-order shaped at the output. Simulation results confirm the second-order noise shaping of the output of the ADC, and an excellent (14-bit signal-to-noise and distortion ratio) performance with the over-sampling ratio of 16.

In this Letter, a new error-resilient router design for network-on-chips (NoCs) is proposed to effectively address various transient errors considering power efficiency and implementation complexity. To cope with the most probable error conditions, a selective error correction code (ECC) is embraced in router design, which combines an optimised double-bit error-correcting Bose–Chaudhuri–Hocquenghem (BCH) code and a single-bit error-correcting Hamming code. To reduce the inherent delay overhead of the BCH code, the parallel BCH coding scheme is designed and implemented into the proposed router. Furthermore, the associated ECC controller is designed for switching into an appropriate ECC mode without an additional delay at runtime. The proposed router is synthesised using 28 nm CMOS technology. Experimental results with a variety of common error conditions show that the proposed method improves the average latency by up to 13.8% and achieves up to 11.5% power reduction with the area increase of 5.7%, when compared to the conventional error correction scheme.

An ultra-low-voltage two-stage dynamic comparator is proposed with a forward body bias (FBB) scheme for successive approximation register (SAR) analogue-to-digital converters (ADCs). The proposed FBB scheme for a preamplifier and latch stage reduces the delay time remarkably under a low supply voltage. At 0.4 V, the power consumption is 4.48 nW, and the delay can be decreased to 593.9 ns for ΔV _in = 0.1 mV and f _clk = 100 kHz. The RMS equivalent input-referred noise of the comparator is 0.136 mV. The total offset is 13.7 mV, and offset fluctuation is 0.183 mV with the proposed structure. Both the input-referred noise and offset fluctuation are <0.5 least-significant bit for a 10-bit SAR ADC at 0.4 V.

A vertically symmetric lumped element directional coupler (VSLEDC) providing broadband characteristics is proposed. In simulations, the proposed VSLEDC showed a 43.8% broader bandwidth than a horizontally and vertically symmetric lumped element directional coupler under similar design conditions for the same insertion loss. The proposed coupler was implemented in a Global Foundry 130 nm CMOS technology. The overall chip size was 1300 µm × 850 µm. The coupling was designed to be −10 dB at 1 GHz. The S-parameter measurements showed an absolute bandwidth and a fractional bandwidth of 141.1 MHz and 14.11%, respectively. Within the bandwidth, the insertion loss was 1.6‒1.8 dB.

This Letter suggests a novel method for improving the robustness and the geometric transformation modelling capability in multi-view convolutional networks (MVCNNs). First, the deformable convolutional networks are used to learn more details and features related to the geometric transformation which the standard convolutional neural networks cannot handle. Then a view-pooling layer is specifically designed for combining the descriptors from multiple views as the final representations of the 3D shapes. The key idea is to insert the deformable convolutional layer between the input and convolutional layer, making it possible to solve deformable 3D shape classification problems, which was a challenging task for MVCNN framework. The proposed method achieves state-of-the-art classification results on two subsets of the ModelNet dataset (ModelNet10 and ModelNet40) over previous methods by a significant margin.

Recently deep learning-based methods for dense depth completion from sparse depth data have shown superior performance than traditional techniques. However, sparse depth data lose the details of the scenes, for instance, the spatial and texture information. To overcome this problem, additional single image is introduced and a multi-scale features fusion scheme to learn more correlations of the two different data is proposed. Furthermore, sparse convolution operation to improve feature robustness for sparse depth data is exploited. Experiments demonstrate that the approach obviously improves the performance for depth completion and outperforms all the previous published methods. The authors believe their works also have the guidance significance for stereo images depth estimation fused with sparse LiDAR depth data.

In this Letter, harmony search (HS) technique hybridised with genetic algorithm (GA) is proposed. This technique mainly takes HS direction estimation mechanism and genetic operators in GA, which significantly increase the convergence of the HS algorithm. Specifically, the authors propose to incorporate main operators of GA into the HS algorithm to avoid some inherent drawbacks of the HS. For example, crossover is incorporated into HS to deal with low accuracy problem, while mutation is incorporated to escape from the local optimum solutions. In addition, elitism is introduced into the HS, to precipitate the performance and prevent the loss of favourable individuals found during the search process. The authors compare the performance of the GA, HS, and other popular HS variants on several benchmark functions. Numerical results show that the proposed hybridisation exhibits a superior performance in comparison to other algorithms.

In spread spectrum (SS) communications, the input signal is spread over a wider bandwidth to avoid interference or interception. One of the most common SS techniques is direct sequence SS (DSSS). In this Letter, the authors propose non-cooperative compressive detection techniques for DSSS signals. The proposed compressive detection framework allows the use of random as well as designed measurement kernels. A technique for designing compressive measurement kernels which exploit DSSS signal structure and non-uniform usage of spreading codes is proposed. Theoretical and simulation results are provided to compare the performance of the proposed methods with their conventional counterparts.

In this Letter, the authors derive the closed-form formulas for the generalised moment generating function of the Fisher–Snedecor (F–S ) distribution, which enable us to effectively evaluate the probability of successful secure transmission over F–S composite fading channels. Extensive numerical results are presented to validate the accuracy of their analytical framework.

A novel high-efficiency and noise-robust differential chaos shift keying (DCSK) communication approach based on an analytically solvable chaotic oscillator (ASCO) is proposed. Due to the special characteristic of the ASCO that provides predictability over specific intervals of every binary symbol period, the proposed communication system requires no reference signal like conventional DCSK systems, which can double the data transmission rate. Meanwhile, the originally transmitted binary information can be recovered by conducting integration processing of the received signal over the specific intervals of every binary symbol period, even under strong noise conditions, which provides a low bit error rate (BER). Simulations are conducted to verify that the proposed DCSK approach provides a much lower BER than conventional DCSK approaches.

Iterative localisation is currently arising as a solution to localise a mobile station in a cellular network. It is shown recently that iterating between the conventional delay estimation and multi-lateration steps allows one to approach the performance of direct localisation algorithms. Until now, the method has only been applied to the case of networks where the access points (APs) are perfectly synchronised with each other. A localisation and time synchronisation iterative algorithm suitable for networks is presented, where APs are not synchronised. It is shown numerically that iterating between the two conventional steps brings a significant performance gain.

A novel technique to design substrate integrated waveguide (SIW) resonator with harmonic suppression is proposed. The spurious band arising from the harmonics is designed as well as the fundamental passband. The bandwidth of the spurious band is designed to be zero to realise harmonic suppression. At the same time, the fundamental properties of the SIW are almost not affected, and no additional circuit area is required. The harmonic suppression and the fundamental passband can be designed independently of each other. An SIW resonator with harmonic suppression and an SIW filter with wide stopband are fabricated and measured to verify the proposed technique. The results agree with expectation well.

Proposed is an electrical spectrum synthesis technique that converts low-speed signals to a high-speed signal using transmitter-side digital signal processing (DSP) and an ultra-broadband electrical bandwidth doubler. The transmitter-side DSP converts a high-speed signal to low-speed upper and lower sideband signals, down- and up-converts the low-speed signals into baseband signals, and adds and subtracts the in-phase and the quadrature components of the baseband signals. The digital pre-processed low-speed signals output from digital-to-analogue converters are multiplexed to the high-speed signal by the bandwidth doubler, which consists of analogue multiplexers designed and fabricated using in-house indium phosphide heterojunction bipolar transistor technologies. A 120 GBaud quadrature phase shift keying signal has been successfully generated by using the proposed technique as a demonstration of a high-speed optical transmitter.

The use of optical transceivers in antenna array system applications requires reliable operation at high temperature. The experimental characterisation of a silicon photonics transceiver operating in a harsh environment with temperatures up to 120°C is presented and discussed. The transceiver was placed inside a climatic chamber and it was fed by an external depolarised light source. The bit error rate was measured, and the impacts on transmission performances were analysed and discussed, including reliability aspects. The authors believe that silicon photonics transceivers with an optimised design and with improvements in the optical connector and fibre adhesive technology are suitable for this kind of applications.

Fibre Bragg grating inscription in the crystalline silicon (Si)-core fibre is described using visible light femtosecond laser pulses. The femtosecond pulses at 517 nm propagate through the transparent silica glass cladding and are fully absorbed by the Si core generating locally high temperatures and stress fields in forming the grating periods. The Si FBGs were characterised in reflection, calibrated for a first time as strain and temperature sensors and compared with that of FBGs inscribed in standard silica fibres.

Quantum dot infrared photodetectors (QDIPs) are receiving attention as next generation infrared photodetectors that offer high-sensitivity and high-temperature operation. The realisation of QDIPs on silicon (Si) substrates offer further great advantages in terms of cost reduction and higher-resolution focal plane arrays. Indium arsenide/gallium arsenide QDIPs grown directly on on-axis Si (100) substrates are demonstrated. These are expected to further reduce fabrication costs by utilising both the monolithic integration of QDIPs with Si readout integrated circuits and also the bare substrate cost (compared with offcut Si substrates). In the device, the peak detectivity at a temperature of 32 K is measured to be 5.8 × 10⁷ cm Hz^1/2/W of 6.2 μm at a bias 0.6 V, with a corresponding responsivity of 27 mA/W. This result indicates that QD structures directly grown on on-axis Si substrates are very promising for the realisation of high-performance QDIPs with low fabrication cost.

A hybrid double stator bearingless switched reluctance motor with advantages of high suspension output, small loss and weak coupling is presented. This motor can realise electric/power generation and radial two-degree-of-freedom suspension. The biased magnetic field for producing radial force is provided by a permanent magnet, which reduces system power consumption. Self-decoupling is realised between a torque system and suspension system according to the mechanical structure design. Furthermore, the radial force is approximately constant when the suspension current is constant, thereby improving the controllability of the system. The operation principle is introduced and the electromagnetic characteristics are analysed through the time-stepping finite element method. This analysis verifies the effectiveness of the theoretical analysis.

New high-quality thermoelectric devices with amorphous silicon/magnesium silicide (a-Si/Mg₂Si)-stacked hetero-structure thin film layers have been fabricated using both radio frequency sputtering and rapid thermal annealing techniques. The thermoelectric properties of the a-Si/Mg₂Si hetero-structure layers were found to be much superior to those of the a-Si layer.

In general, theoretical analyses of adaptive filtering algorithms employ statistical approximations in order to render the derivations tractable. Among such hypotheses, the statistical independence between the current adaptive coefficients and past input vectors is a very popular one. Unfortunately, this simplification gives rise to discrepancies with respect to empirical results, especially for large values of the step-size parameter. In this Letter, this issue is overcome by the usage of an exact expectation analysis (i.e. a stochastic model that does not employ the above-mentioned independence assumption) of the least-mean-squares adaptive algorithm. The authors analysis is also generalised in order to address the common case of coloured additive noise, an issue that is so far missing from the literature. The accuracy of the advanced model is verified through simulations.

A Cover Song Identification (CSI) scheme based on non-linear graph fusion and Tensor Product Graphs (TPGs) diffusion is proposed as an improvement to the authors' previously proposed similarity fusion-based CSI scheme. First, the harmonic progression, melody evolution, and rhythm-based descriptors are extracted from the track, respectively. Next, Similarity Network Fusion is adopted to fuse the similarity graphs obtained based on two types of descriptors to take full use of the common as well as complementary properties between them. Finally, TPGs diffusion is performed on the obtained fused similarity graphs to take advantage of the manifold structure contained in them to improve the performance, further. Experimental results demonstrate the superiority of the proposed scheme over their previously proposed one, in terms of identification accuracy and clustering performance.

RF fingerprinting is an emerging technology for identifying hardware-specific features of wireless transmitters and may find important applications in wireless security. In this study, the authors present a new RF fingerprinting scheme using deep neural networks. In particular, a long short-term memory based recurrent neural network is proposed and used for automatically identifying hardware-specific features and classifying transmitters. Experimental studies using identical RF transmitters showed very high detection accuracy in the presence of strong noise (signal-to-noise ratio as low as dB) and demonstrated the effectiveness of the proposed scheme.

A novel transceiver architecture is proposed to mitigate the phase noise in the prevailing wireless full-duplex transceivers. In this architecture, an oscillator module is designed to generate both the transmitter and the receiver oscillator signals from one single oscillator. Particularly, a digitally-controlled delay module is used to control the delay of the receiver oscillator signal before mixing with the received signal at the down converter. By adjusting the delay value of the receiver oscillator signal, the power of residual self-interference (SI) after digital SI cancellation can be minimised. Analytical and simulation results show that the digital SI cancellation capability of the proposed architecture can be 18 dB better than that of the conventional architecture of sharing one oscillator for transmitter and receiver.