A new geometry of compact wideband/dual-band circularly polarised dielectric resonator antenna (DRA) is presented. First, a wideband DRA is realised by a rectangular dielectric resonator excited by a vertical coaxial probe feed which is supported by a small substrate. Circular polarisation is achieved by utilising a configuration of the DRA feed that excites orthogonal modes inside the DRA. A 3 dB axial-ratio bandwidth of about 20.8% (9.05–11.14 GHz) is achieved. Second, extension to dual-band circularly polarised operation is then realised by additionally removing a corner of the rectangular DRA at 45° and adding a floating parasitic strip. The experimental results demonstrate an impedance bandwidth of about 59.8% (6.57–12.18 GHz) and the dual 3 dB axial-ratio bandwidths of about 10.6% (8.31–9.24 GHz) and 13.5% (10.18–11.66 GHz). The measured peak gain varies from 4.47 to 4.86 dBiC in the lower band and 4.33 to 4.91 dBiC in the upper band.

A new terahertz (THz) filtering antenna realised by 3D substrate integrated circular waveguide (3D-SICW) is presented. The filtering antenna is designed on a low-temperature co-fired ceramic substrate. Different from traditional planar structure, the direction of power in 3D-SICW is along Z-axis and this will significantly enhance the performance of the devices at THz frequency. The filtering antenna is constructed by two 3D-SICW cavities and a standard substrate integrated waveguide (SIW) cavity, where one SICW cavity and the standard SIW cavity form the bandpass filter by using electric coupling and the other SICW cavity is used as antenna. The results indicate that the passband of filtering antenna range from 170.4 to 177.8 GHz and the gain of antenna is about 5.7 dB. Finally, the filtering antenna is fabricated and measured to verify the simulation prediction. The measured and simulated results are in good agreement at such high frequency.

On the brink of an infectious disease epidemic, contact tracing must be precisely focused on those most likely to have made contacts with the confirmed cases. This explores if the tracing can be made fine-grained enough for train riders, so that those sharing the same car are identified as higher priority contact tracing targets, over those on different cars.

Highly optimised reconfigurable hardware architecture is proposed of 64 bit block ciphers MISTY1 and KASUMI for wide-area cryptographic applications. The reconfigurable hardware architecture is comprised of reconfigurable components consisting of FL function, FO/FI function and XOR function designed to perform MISTY1 and KASUMI algorithms round transformation functions. In addition, reconfigurable FO/FI function is adequate to generate MISTY1 extended keys for onward use in MISTY1 round transformation function. The substitution functions S9 and S7 for MISTY1 and KASUMI algorithms are optimised for area and throughput. Common sub-expression elimination for AND-XOR logic combined with permutation/combination technique for AND gates reduces the area considerably, whereas parallel execution improves the throughput. With this design approach, application specific integrated circuit (ASIC) implementations using Synopsys Design Complier, SMIC 0.18 µm at 1.8 V achieved an area of 3481 NAND gates having throughput of 130.2 and 154.56 Mbits/s for MISTY1 and KASUMI, respectively. Synthesised FPGA implementation using Xilinx Artix 7 FPGA yielded an area of 487 configurable logic block (CLB) Slices having throughput of 209.43 and 248.7 Mbits/s for MISTY1 and KASUMI, respectively. Detailed design and performance analysis of reconfigurable hardware architecture of 64 bit block ciphers MISTY1 and KASUMI for ASIC implementations is described.

Recently, multi-level cell (MLC) spin-transfer torque random access memories (STT-RAMs) are attracting great attentions as an alternative to static or dynamic random access memories. They have the benefits of capacity, but the penalties of performance, and power consumption caused by a complicated two- or three-phase access. An MLC STT-RAM controller that eliminates the MLC STT-RAM penalties for multimedia applications is proposed. The key ideas are frame-level data-to-memory mapping and frame-type aware frame assignment techniques that make a two- or three-phase access no longer required. Experimental results show that the proposed MLC STT-RAM controller achieves 56.1% higher memory performance, and 4.2% lower memory power consumption than the conventional controller for industrial multimedia applications.

A new multistage 1-1 ΔΣ analogue-to-digital converter (ADC) architecture implemented only with voltage-controlled oscillators (VCOs) is introduced. A sturdy multistage noise-shaping (SMASH) configuration is used to avoid the need of either calibration circuitry or noise-cancellation filters. The digital nature of the VCO's output simplifies the implementation of the interconnection paths between stages, making unnecessary neither the use of multibit digital-to-analogue converters nor analogue subtraction elements. The basic operation of the architecture is shown at system level and the sensitivity to VCO's frequency mismatch is analysed. The proposed architecture has been validated through behavioural simulations.

A dual correlated double sampling (CDS) scheme, which can be embedded into a successive approximation register (SAR) or SAR/single-slope analogue-to-digital converters (ADCs) for low-noise CMOS imagers without the use of a power-consuming programmable gain amplifier (PGA) is proposed. To reduce the noise of the readout channel, the proposed dual CDS scheme removes the sampling error, which occurs in the capacitor digital-to-analogue converter (DAC), by storing only a reset voltage of the pixel into the capacitor DAC. In addition, without using the PGA, it amplifies the output of the readout channel by controlling the reference voltages of the ADC. The readout channel using the proposed CDS scheme was designed using a 90 nm CMOS imager process technology. The simulation results show that the signal-to-noise-distortion ratio of the readout channel using the proposed dual CDS scheme is 81.8 dB, which is an improvement of 10.8 dB over the digital CDS scheme. In addition, the output of the readout channel is amplified without the use of a PGA.

By block compressed sensing (BCS), the image can be compressed and encrypted simultaneously. A novel reversible data hiding (RDH) method is proposed to embed additional data into the BCS encrypted images. In the proposed method, based on the image block edge pixel separation, every block can be used for data embedding through a special measurement flipping. After decryption, considering the correlation of natural images, the fluctuation function can be used to find out the flipped block and realise the data extraction and image recovery. Experiments show that the proposed method can outperform the existing RDH method in BCS images.

Self-similarity is an attractive image property that has been successfully applied to object recognition due to its robustness to severe target appearance variations. However, less attention has been paid to explore self-similarity for visual tracking, mainly because it is difficult to learn self-similarity information between different features suitable for visual tracking. To address this issue, a simple, yet effective approach is presented to learn self-similarity information among the local features extracted from the different regions of the target. The target is first divided into some non-overlapping regions, in which each region is described by the histogram of gradient (HOG) features. Then, an explicit polynomial kernel feature map is constructed, which is capable of characterising the self-similarity information among all the local regions in the targets. Finally, based on the feature maps, a linear support vector machine (SVM) is learnt via an online dual coordinate descent method that offers fast convergence guarantee. Experiments on a large tracking benchmark dataset with 50 sequences demonstrate the superiority of the proposed method over state-of-the-art methods.

In an interactive image segmentation, the quantity of a user-given seed is known to affect the segmentation accuracy. In this Letter, we propose a seed-growing method expanding the quantity of a seed to reduce the bias of the given seed and improve the segmentation accuracy. To grow the given seed, a supervised classification framework with geodesic distance features is proposed. From a single input image, a support vector machine (SVM) classifier is trained on the seed superpixels of an input image. Other non-seed superpixels are then classified into object, background and non-seed regions by the trained classifier. In experiments, the proposed method showed promising results by improving the segmentation accuracy of existing segmentation methods in public benchmark datasets.

A simple and effective method for visual saliency detection in colour images is presented. The method is based on the common observation that local salient regions exhibit distinct geometric and texture patterns from neighbouring regions. The colour distribution of local image patches is modelled with a Gaussian density and measure the saliency of each patch as the statistical distance from that density. Experimental results with public datasets and comparison with other state-of-the-art methods show the effectiveness of the method.

A novel hopping discrete Fourier transform (DFT) algorithm and its architecture design for efficiently computing time–frequency spectra are presented. Since the sliding process is adopted sample by sample, the spectral bin output data rate is the same as the input data rate. Under the conditions of an M-sample complex input sequence (M = 256), and N-point recursive DFT computation (N = 64) for time hop L (L = 4), the proposed method has the following advantages: (i) the computational complexity of Proposed-I requires only four complex additions and four complex multiplications for each frequency bin, after the first spectral component has been finally calculated; (ii) Proposed-II utilises a re-timing scheme to greatly shorten and balance the critical path; (iii) Proposed-II is less computationally complex than Wang et al.’s method, as the numbers of multiplication and addition operations in the proposed algorithm are 768 and 1024, representing reductions of 50 and 20%, respectively. In addition, the number of coefficients can be reduced by 50% compared with Park et al.’s method. In the FPGA implementation, the proposed design can be operated at 47.26 MHz. It is thus more suitable for use with real-time analytic applications of time–frequency spectra.

A generalised Pollaczek–Khinchin formula for the Polya/G/1 queue, with a Polya peaked arrival process, general distributed service times, and infinite number of waiting positions, is obtained. It is shown that the peakedness of the number of arrivals and the variance of the service time lead to a significant increase in the service delay and queue length.

An (n = 2k + s,k) Suh–Ramchandran code is shown, where s > 0 is a positive integer, is a minimum storage regeneration code, and can also achieve the optimal repair bandwidth for multiple systematic nodes failure repair.

A novel extension of the cubic phase function (CPF), known as the parameterised centroid frequency-chirp rate distribution (PCFCRD), is proposed for multicomponent linear frequency modulated signals analysis. The PCFCRD is coherent and introduces a constant delay to reduce the noise correlation. Mathematic analysis and numerical simulations demonstrate that, compared with the coherent integrated CPF, the PCFCRD can obtain a higher anti-noise performance.

In device-to-device (D2D) underlaying cellular networks, interference generated by D2D communications can be exploited to improve secrecy rate of cellular users (CUE). The security-oriented distributed access selection algorithm is proposed, in which each D2D pair decides whether to access to radio resources according to its local channel state information without considering the locations of D2D pairs and Eve. The ergodic secrecy rate of CUE and the data rate of D2D pairs in the proposed scheme are investigated. Simulation results show that the proposed scheme can achieve an impressive secrecy performance gain.

The design of a planar microstrip coupler where power coupling between two parallel microstrip lines can easily be controlled is presented. Enhancement of power coupling is done via two small slots in the ground plane underneath the microstrip pair. The ground plane slots force the field lines near the edge of each microstrip to cross to the adjacent microstrip. The magnitude of the power coupling can easily be controlled by adjusting the length of the slots. Here, the operation of a microstrip coupler is described, and the design of a 1 × 4 power distributor array that can be used to distribute the input microwave power uniformly to four branch lines arranged in a row is presented. The measured responses of the array are also presented, and shown that the performance agree very well with simulated results.

The electromagnetic and mechanical performance of microstrip lines integrated into aerospace composite structure is discussed. The microstrip lines were manufactured using either an embroidery (with a conductive thread) or stencil transfer (with a conductive veil) technique. Both manufacturing techniques are fully compatible with existing aerospace pre-preg materials and autoclave processing. The embroidered microstrip line exhibited superior electromagnetic performance over the veil microstrip line. However, the electromagnetic performance of the embroidered microstrip line deteriorated rapidly when mechanically deformed unlike the veil microstrip line. Both manufacturing techniques resulted in a reduction of the maximum flexural stress at failure for the multifunctional composite. This suggests a trade between electromagnetic performance and mechanical durability governs which manufacturing approach is better suited to the integration of microwave componentry (such as antennas and feed networks) into aerospace composite structure.

A Ka-band push–push voltage-controlled oscillator (VCO) using a parasitic capacitance cancelling technique is presented. To enhance the oscillation frequency (f _osc) and the tuning range (TR), the parasitic capacitance of the VCO is cancelled with negative capacitance (NC). To realise NC, a negative impedance circuit (NIC) is analysed and designed. Because of self-resonance frequency, NC is realised using an open-circuit stable NIC. For further enhancement of the f _osc, the VCO is developed in a push–push operation. The proposed VCO is fabricated in a commercial 0.15 μm GaAs pHEMT process. It shows 12.4% of the TR at 31.6 GHz with 11 dBm output power. With the NIC, the centre frequency of the VCO increases from 20.1 to 31.6 GHz and the TR increases from 5.7 to 12.4% compared with a VCO without the NIC.

GaSb-based type-I quantum wells cascade diode lasers with nearly diffraction limited output beam were fabricated using methane–hydrogen dry etching plasma process. Rapid thermal annealing was shown to be a necessary step to reverse the effect of hydrogen plasma on conductivity of AlGaAsSb cladding alloy. Annealed two-step narrow ridge lasers confined both optical field and current in lateral direction and demonstrated operating voltage, threshold current density and slope efficiency comparable to those of reference wide ridge devices.

A datasheet-based fully detailed model for nonlinear capacitances is proposed to significantly reduce the simulation time on the turn-on and turn-off transitions of power electronic circuits. In this model, a nonlinear capacitance is Thévenin equivalent to a voltage source in series with a constant resistance, and the nonlinear part is represented in the voltage source. So, unchangeable admittance matrix is achieved regarding the nonlinear part of capacitances as excitations. Appreciable calculation speedup is gained while good accuracy is maintained.

A model predictive current control scheme with dc-link capacitor voltages fluctuation suppression for the four-switch three-phase rectifier (FSTPR) in balanced grids is presented. The proposed control scheme is a type of the finite-control-set model predictive control scheme and is based on the discrete-time model of the system. From this model, the values of input currents and dc-link capacitor voltages are predicted for all switching states of the FSTPR. On the basis of a predefined cost function, the switching state, which minimises the errors between input currents and their references as well as the difference between two dc-link capacitor voltages at the next sampling instant, is selected. Simulation results are presented to confirm the effectiveness of the proposed control scheme.

The electron transport properties of an electrostatic gated single molecular transistor are investigated by using self-consistent semi-empirical method. The charge transport characteristics of the molecular device are analysed through the current-voltage I _SD−V _SD characteristics transmission characteristics T (E), and molecular projected self-consistent Hamiltonian states analysis. It is revealed that the gate bias V _G can effectively tune the transport properties to greater extent. The mechanisms governing the gate bias tuned transport properties in this device were discussed. The proposed device also exhibits gate modulated negative differential resistance feature, which is exploited in realising basic logic gates. Thus, by using source-drain resistance R as a function of V _G, the application of using gated thiophene based molecular device to realise a set of five basic logic gates at particular V _SD is shown. The significant feature of the proposed device is the possibility of realising different logic gates with just one molecular transistor using computationally inexpensive semi-empirical method.

Mobile data collection is one of research highlights for sparse three-dimensional underwater sensor networks. Therein, optimal or near-optimal cruise trajectory planning of mobile sink is very crucial. A 3D Dubins curves based continuous path programming algorithm (GA-3DTSP in short) for underwater mobile sink with non-holonomic constraints such as well-known autonomous underwater vehicle is proposed. The objective of GA-3DTSP algorithm is to trace sparsely deployed sensor nodes by mobile sink so as to achieve near-optimal energy conservation efficiency. First, an extended 3D Dubins curve is proposed and the length calculation formulae for 3D Dubins curve are investigated. Furthermore, genetic algorithm is used to tackle this difficult NP-complete problem of planning shortest paths in a heuristic manner. Finally, simulation results verify that the proposed GA-3DTSP method can conserve cruise energy of mobile sink effectively.

Neyman–Pearson detection method is presented for a cluster-based wireless sensor network (WSN) massive multiple-input multiple-output (MIMO) system. In this scenario, the sensors are divided into K clusters in which the number of clusters is smaller than the number of receivers antennas. A closed-form optimal solution is derived for the gain of each sensor. Simulation results show that for a constant total transmit power in the network, the probability of detection of the proposed method outperforms the corresponding methods addressed by Jiang et al.