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Fault tolerance and self-checking techniques in microprocessor-based system design

Fault tolerance and self-checking techniques in microprocessor-based system design

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Fault tolerant design is receiving considerable attention at present in order to safeguard against improper operation of digital systems in critical applications. A number of multiprocessor systems featuring hardware fault tolerance are now available commercially. The paper presents an overview of some of the work done so far in the application of fault tolerance techniques to improve the reliability and availability of microprocessor-based systems. An alternative approach to enhance the reliability of a system is to apply self-checking techniques, primarily through the use of error detecting codes. By merging the fault tolerance and the self-checking techniques, the reliability and the maintainability of microprocessor-based systems can be significantly improved.

References

    1. 1)
      • J.F. Wakerly . Transient failures in triple modular redundancy systems with sequential modules. IEEE Trans. , 570 - 572
    2. 2)
      • P.K. Lala . (1984) , Fault-tolerant and fault-testable hardware design.
    3. 3)
      • D.A. Anderson , G. Metze . Design of totally selfchecking check circuits for m-out-of-n codes. IEEE Trans. , 263 - 269
    4. 4)
      • Lewis, D.W.: `A fault-tolerant clock using stand-by sparing', Proceedings of ninth international symposium on fault tolerant computing, 1979, p. 33–40.
    5. 5)
      • Maki, G.: `Design of microprocessors for self fault detection', 1977, p. 236–240, IEEE Microcomputer Conference Record.
    6. 6)
      • McCluskey, E.J., Wakerly, J.F.: `A circuit for detecting and analysing temporary failures', Proceedings of ieee compcon conference, 1981, p. 317–321.
    7. 7)
      • Siewiorek, D.: `Reliability modelling of compensating module failures in majority voted redundancy', Proceedings of fourth international symposium on fault tolerant computing, 1974, p. 214–219.
    8. 8)
      • D. Siewiorek . A case study of C-mmp, Cm and C.vmp. Part I: Experiences with fault-tolerance in multiprocessor systems. Part II: Predicting and calibrating reliability of multiprocessor systems. Proc. IEEE , 1178 - 1220
    9. 9)
      • D. Davies , J.F. Wakerly . Synchronisation and matching in redundant systems. IEEE Trans. , 531 - 539
    10. 10)
      • D. Johnson . The Intel 432: a VLSI architecture for faulttolerant computer systems. IEEE Computer , 40 - 48
    11. 11)
      • Lee, E.T., Lee, N.: `Design of a fault- tolerant microprocessor', Proceedings of ieee compcon fall, 1979, p. 100–105.
    12. 12)
      • Wakerly, J.F.: `Design of a self-checking microprogrammed processor1', Proceedings of sixth international symposium on fault tolerant computing, 1976, p. 191.
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