The comparative cost of associative memory

Access Full Text

The comparative cost of associative memory

For access to this article, please select a purchase option:

Buy article PDF
£12.50
(plus tax if applicable)
Buy Knowledge Pack
10 articles for £75.00
(plus taxes if applicable)

IET members benefit from discounts to all IET publications and free access to E&T Magazine. If you are an IET member, log in to your account and the discounts will automatically be applied.

Learn more about IET membership 

Recommend Title Publication to library

You must fill out fields marked with: *

Librarian details
Name:*
Email:*
Your details
Name:*
Email:*
Department:*
Why are you recommending this title?
Select reason:
 
 
 
 
 
Radio and Electronic Engineer — Recommend this title to your library

Thank you

Your recommendation has been sent to your librarian.

The production cost-per-bit of high-speed associative memory, implemented with m.o.s. l.s.i. content addressable memory (c.a.m.) devices (selected from a survey of 20 designs), is compared with that of conventional memory, implemented with currently available m.o.s. l.s.i. random access memory (r.a.m.) devices.For a development cost of about £20k, the cost-perbit of the m.o.s. c.a.m.s is about 5× that of a 1024-bit p-channel m.o.s. dynamic r.a.m. and about 9× that of a 4096-bit n-channel m.o.s. dynamic r.a.m., if plastic dual-in-line packaging is employed. However, for open-chip (beam-lead or flip-chip) assembly the cost-per-bit of the m.o.s. c.a.m.s is less than 2× that of the 1024-bit r.a.m. and less than 3× that of the 4096-bit r.a.m.It is shown that for most associative processing applications the associative memory can provide a cheaper alternative to conventional r.a.m.-based computer systems.

Inspec keywords: field effect integrated circuits; integrated memory circuits; content-addressable storage; large scale integration

Other keywords: content addressable memory; RAM devices; MOS LSI devices; production cost per bit; high speed associative memory

Subjects: Memory circuits; Semiconductor storage; Other MOS integrated circuits

References

    1. 1)
      • C.J. Shead . The associative memory: a versatile circuit element. GEC J. Sci. Tech. , 3 , 119 - 125
    2. 2)
      • B.T. Murphy . Cost-size optima of monolithic integrated circuits. Proc. IEEE , 1537 - 1545
    3. 3)
      • Kaiser, H.W., Collins, T.L.: `A micropower associative processor building block', IEEE Intercon Digest of Tech. Papers, March 1972, p. 52–53.
    4. 4)
      • A.G. Dingwall . High-yield processing for fixed-interconnect large-scale integrated arrays. IEEE Trans. on Electron Devices , 631 - 637
    5. 5)
      • A.G. Hanlon . Content addressable and associative memory systems—a survey. IEEE Trans. on Electronic Computers , 509 - 521
    6. 6)
      • J.T. Koo . Integrated-circuit content addressable memories. IEEE J. Solid-State Circuits , 5 , 208 - 219
    7. 7)
      • D.P. Spampinato . F.e.t. associative memory cell. IBM Tech. Disclosure Bull. , 10 , 1634 - 1635
    8. 8)
      • R.M. Lea . A design for a low-cost high-speed m.o.s. associative memory. The Radio and Electronic Engineer , 4 , 177 - 182
    9. 9)
      • C-m.o.s. content-addressable memory holds 8 8-bit words. Electronics
    10. 10)
      • B. Parhami . Associative memories and processors: an overview and selected bibliography. Proc. IEEE , 722 - 730
    11. 11)
      • G.E. Moore . What level of l.s.i. is best for you. Electronics , 126 - 130
    12. 12)
      • R.M. Lea . Information processing with an associative parallel processor. IEEE Computer , 25 - 32
    13. 13)
      • J.R. Burns , J.H. Scott . Silicon-on-sapphire complementary m.o.s. circuits for high speed associative memory. Proc. AFIPS (FJCC) , 469 - 477
    14. 14)
      • R. Igarashi , T. Yaita . An integrated m.o.s. transistor associative memory system with 100 ns cycle time. Proc. AFIPS (SJCC) , 499 - 506
    15. 15)
      • Mundy, J.L., Joynson, R.E.: `A high density m.o.s. associative memory', Proc. IEEE Computer Society Conf., 1971, p. 179–190.
    16. 16)
      • G. Carlstedt , G.P. Petersson , K.O. Jeppson . A content-addressable memory cell with m.n.o.s. transistors. IEEE J. Solid-State Circuits , 5 , 338 - 343
    17. 17)
      • J.J. Montren . Mosfet associative memory cell. IBM Tech. Disclosure Bull. , 10 , 1632 - 1633
    18. 18)
      • J.E. Price . A new look at yield of integrated circuits. Proc. IEEE , 1290 - 1291
    19. 19)
      • Koo, J.T.: `Integrated circuit content addressable memories', ISSCC Digest of Tech. Papers, February 1970, p. 72–73.
    20. 20)
      • R.M. Lea . Low-cost high-speed associative memory. IEEE J. Solid-State Circuits , 3 , 179 - 181
    21. 21)
      • Igarashi, R., Kurosawa, T., Yaita, T.: `A 150 nanosecond associative memory using integrated m.o.s. transistors', ISSCC Digest of Tech. Papers, February 1966, p. 104–105.
    22. 22)
      • J. Minker . An overview of associative or content-addressable memory systems and a kwic index to the literature—1956–1970. Computing Review , 453 - 504
    23. 23)
      • Mundy, J.L., Burgess, J.F., Joynson, R.E., Neugebauer, C.A.: `Low cost associative memory', ISSCC Direst of Tech. Papers, February 1972, p. 58–59.
    24. 24)
      • L.D. Wald . An associative memory using large-scale integration. NAECON Record , 277 - 281
    25. 25)
      • J.L. Mundy , J.F. Burgess , R.E. Joynson , C. Neugebauer . Low cost associative memory. IEEE J. Solid-State Circuits , 5 , 364 - 369
    26. 26)
      • Lea, R.M.: `Toward a low-cost cell design for high-speed m.o.s. associative memories', Datafair Research Papers, 1973, 11, p. 418–424.
    27. 27)
      • R.M. Lea . Design for a high-speed m.o.s. associative memory. Electronics Letters , 15 , 391 - 393
    28. 28)
      • Herlein, R.F., Thompson, A.V.: `An integrated associative memory element', ISSCC Digest of Tech. Papers, February 1969, p. 42–43.
http://iet.metastore.ingenta.com/content/journals/10.1049/ree.1976.0072
Loading

Related content

content/journals/10.1049/ree.1976.0072
pub_keyword,iet_inspecKeyword,pub_concept
6
6
Loading