Your browser does not support JavaScript!
http://iet.metastore.ingenta.com
1887

Low-power semiconductor memory cell

Low-power semiconductor memory cell

For access to this article, please select a purchase option:

Buy article PDF
£12.50
(plus tax if applicable)
Buy Knowledge Pack
10 articles for £75.00
(plus taxes if applicable)

IET members benefit from discounts to all IET publications and free access to E&T Magazine. If you are an IET member, log in to your account and the discounts will automatically be applied.

Learn more about IET membership 

Recommend Title Publication to library

You must fill out fields marked with: *

Librarian details
Name:*
Email:*
Your details
Name:*
Email:*
Department:*
Why are you recommending this title?
Select reason:
 
 
 
 
 
Proceedings of the Institution of Electrical Engineers — Recommend this title to your library

Thank you

Your recommendation has been sent to your librarian.

Because of its low power dissipation and small area, the dynamic semiconductor random-access memory cell is currently becoming widely used in computer main-memory applications. This paper describes an alternative bipolar memory cell which uses the small area and high yield obtainable with the collector-diffusion isolation process, without the disadvantages of the refresh requirement of dynamic memories. A ratio of 15:1 in power dissipation between the selected and the unselected state allows a large number of storage cells on a single silicon chip, while retaining a relatively fast cycle time.

References

    1. 1)
      • Bruchez, J.A.: `The effect of variation of diffusion profiles and epitaxial layer characteristics on the performance of collector diffused isolated devices', Proceedings of 4th annual conference on solid-state devices, 1970, Lancaster.
    2. 2)
      • J.A. Bruchez . (1969) Application of new isolation technique to digital integrated circuits, Microelectronics.
    3. 3)
      • B.T. Murphy , V.J. Glinski . Transistor-transistor logic with high packing density and optimum performance at high inverse gain. IEEE J. Solid-State Circuits , 261 - 267
http://iet.metastore.ingenta.com/content/journals/10.1049/piee.1973.0246
Loading

Related content

content/journals/10.1049/piee.1973.0246
pub_keyword,iet_inspecKeyword,pub_concept
6
6
Loading
This is a required field
Please enter a valid email address