Design of asynchronous multilevel sequential circuits

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Design of asynchronous multilevel sequential circuits

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A 7-step algorithm for the design of sequential circuits is described. Its use enables engineering constraints such as gate-speed tolerances and fan-in restrictions to be met systematically, and it has been found helpful in meeting system modifications effectively at the design stage. The algorithm is developed with particular reference to NOR circuits; NAND circuits and relay circuits are treated briefly in Appendixes.

Inspec keywords: logic design; asynchronous sequential logic; logic circuits; sequential circuits

Other keywords: Boolean reduction; fan in restrictions; gate speed tolerances; signal substitution; primitive sequential equations; design; relay circuits; gate minimality; NOR circuits; merging; NAND circuits; asynchronous multilevel sequential circuits

Subjects: Logic design methods; Pulse circuits; Digital electronics

References

    1. 1)
      • F.G. Duncan , D. Zissos . Gate tolerences in sequential circuits. Proc IEE. , 2 , 317 - 320
    2. 2)
      • D. Zissos , F.G. Duncan . Fan-in restrictions in logic circuits. Proc IEE , 2 , 321 - 327
    3. 3)
      • D. Zissos . (1972) , Logic design algorithms.
http://iet.metastore.ingenta.com/content/journals/10.1049/piee.1972.0024
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