The paper describes the design of an analogue simulator suitable for sampled-data systems. The basic unit, the zero-order sample and hold, uses field-effect transistors and employs methods which allow a single value of the holding capacitor to be chosen to cover a variation in sample frequencies of 1:6 × 10⁵, consistent with a sample time t_s≥ 1 μs and a hold/sample ratio not greater than 3 × 10⁷, while maintaining an accuracy of within 0.1%. The minimum sample time of the technique described is about 30ns, which compares favourably with a gallium-arsenide-diode bridge technique of greater complexity and having an inferior holding performance. The simulator uses a parallel sequential method of delay and is capable of operating continuously over the sample frequency range 20kHz to 30s per cycle, maintaining an overall accuracy of about 0.37% without recourse to any form of switching. A method of selecting and measuring output levels from the simulator is described which, when used in conjunction with a pen recorder, could produce a problem-solution time of the same order as that produced by a digital-computer program with a graphical output routine. Practical tests are described which show clearly the extent and nature of the small errors which occur during a general simulation.