Efficient logic architectures for CMOL nanoelectronic circuits

Efficient logic architectures for CMOL nanoelectronic circuits

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CMOS molecular (CMOL) circuits promise great opportunities for future hybrid nanoscale IC implementation. Two new CMOL building blocks using transmission gates have been introduced to obtain efficient combinational and sequential logic for CMOL designs. Compared with the existing CMOL circuits, the proposed CMOL designs based on these blocks can achieve more than 30% improvement in speed and up to 80% improvement in density and power consumption while providing similar fault tolerance capabilities. This work significantly advances the applications of CMOL to actual electronic circuits and systems.


    1. 1)
      • K.K. Likharev , D. Strukov , G. Cuniberti . (2005) CMOL: devices, circuits, and architectures, Introduction to molecular electronics.
    2. 2)
    3. 3)
      • Strukov, D.B., Likharev, K.K.: `A reconfigurable architecture for hybrid CMOS/nanodevice circuits', FPGA 06, February 2006, p. 131–140.
    4. 4)
      • K.K. Likharev , A. Mayr , I. Muckra , Ö Türel . CrossNets: high-performance neuromorphic architectures for CMOL circuits. Ann. NY Acad. Sci. , 146 - 163
    5. 5)
      • Likharev, K.K.: `Neuromorphic CMOL circuits', Proc. IEEE-NANO, 2003, p. 339–342.
    6. 6)
      • Strukov, D.B., Likharev, K.K.: `A reconfigurable architecture for hybrid CMOS/nanodevice circuits', FCCM 05.
    7. 7)
      • Ecoffey, S., Pott, V., Mahapatra, S., Bouvet, D., Fazan, P., Ionescu, A.M., Kruit, P., Van Der Drift Emile, W.J.M.: `A hybrid CMOS-SET co-fabrication platform using nano-grain polysilicon wires', Int. Conf. on Micro and Nano Engineering, 2005, 78–79, p. 239–243.
    8. 8)
    9. 9)
    10. 10)
      • A. Dehon . Nanowire-based programmable architecture. ACM J. Emerg. Technol. Comput. Syst. , 109 - 162
    11. 11)
    12. 12)
    13. 13)
      • Butts, M., DeHon, A., Goldstein, S.C.: `Molecular electronics: devices, systems and tools for gigagate, gigabit chips', Proc. Int. Conf. on Computer-Aided Design, 2002, ICCAD'02.
    14. 14)
      • DeHon, A., Likharev, K.K.: `Hybrid CMOS/nanoelectronic digital circuits: devices, architectures, and design automation', IEEE/ACM Int. Conf. on Computer-Aided Design, 2005, p. 375–382.
    15. 15)
      • Ziegler, M.M., Stan, M.R.: `The CMOS/nano interface from a circuits perspective', IEEE Int. Symp. on Circuits and Systems, 2003, 4, p. 904–907, ISCAS'03.
    16. 16)
    17. 17)
      • S. Mahapatra , A.M. Ionescu . Realization of multiple valued logic and memory by hybrid SET-MOS architecture. IEEE Trans. Nanotechnol. , 705 - 714
    18. 18)
      • J.M. Rabaey . (1996) Digital integrated circuits: a design perspective.

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