In this work, the authors propose and simulate a double L-shaped gate tunnel field-effect transistor (DLG-TFET) with the covered source–channel. The proposed structure improves the ON-state current by increasing the linear tunnelling area and has excellent subthreshold characteristics. The simulation focuses on the performance improvement of the device under different longitudinal gate length L _g, interlayer silicon thickness T _si, gate and source overlap length L _ov, and covered source depth L _s. For optimal parameters, the ON-state current of the proposed DLG-TFET increases up to 3.53 × 10⁻⁵ A/μm, and the current switch ratio(I _on/I _off) is 4.28 × 10¹¹ at room temperature, moreover, a minimum subthreshold swing (SSmin) and an average subthreshold swing (SSave) are as low as 32.2 and 52.9 mV/Dec, respectively. Meanwhile, this work uses mixed device-circuit simulations to predict the performance of the inverter circuit implemented with proposed DLG-TFET.