Cadmium sulphide and titanium dioxide-based junctionless transistor (JLT) has been demonstrated by using simple and low-cost chemical bath deposition method. The morphological and structural study has been performed to speculate the crystallinity and the topography of individual layers of the proposed device. The optimised sputtering conditions lead to the formation of source and drain electrical contacts of the device. The fabricated device successfully functionalised as a p-channel JLT. At the source-to-drain voltage of −50 V, the ON-state drive current and OFF-state leakage current of the fabricated JLT are found to be −6 µA and 1.3 nA, respectively.

References

1. 1)
  - 19. Saremi, M., Afzali-Kusha, A., Mohammadi, S.: ‘Ground plane fin-shaped field effect transistor (GP-FinFET): a FinFET for low leakage power circuits’, Microelectron. Eng., 2012, 95, pp. 74–82 (doi: 10.1016/j.mee.2012.01.009).
2. 2)
  - 22. Majumder, S., Baviskar, P.K., Sankapal, B.R.: ‘Light-induced electrochemical performance of 3D-CdS nanonetwork: effect of annealing’, Electrochim. Acta, 2016, 222, pp. 107–100 (doi: 10.1016/j.electacta.2016.10.147).
3. 3)
  - 6. Patil, G.C., Qureshi, S.: ‘Engineering spacers in dopant-segregated Schottky barrier SOI MOSFET for nanoscale CMOS logic circuits’, Semicond. Sci. Technol., 2012, 27, pp. 045004–045012 (doi: 10.1088/0268-1242/27/4/045004).
4. 4)
  - 9. Duarte, J.P., Choi, S.-J., Choi, Y.-K.: ‘A full-range drain current model for double-gate junctionless transistors’, IEEE Trans. Electron Devices, 2011, 32, (6), 704–706 (doi: 10.1109/LED.2011.2127441).
5. 5)
  - 14. Zhao, D., Nishimura, T., Lee, C.H., et al: ‘Junctionless Ge p-channel metal–oxide–semiconductor field-effect transistors fabricated on ultrathin Ge-on-insulator substrate’, Appl. Phys. Express, 2011, 4, p. 031302 (doi: 10.1143/APEX.4.031302).
6. 6)
  - 20. Sankapal, B.R., Gajare, H.B., Dubal, D.P., et al: ‘Presenting highest supercapacitance for TiO2/MWNTs nanocomposites: novel method’, Chem. Eng. J., 2014, 247, pp. 103–111 (doi: 10.1016/j.cej.2014.02.092).
7. 7)
  - 16. Su, C.J., Tsai, T.I., Liou, Y.L., Lin, Z.M., Lin, H.C., Chao, T.S.: ‘Gate-all-around junctionless transistors with heavily doped polysilicon nanowire channels’, Electron Device Lett., 2011, 32, pp. 521–523 (doi: 10.1109/LED.2011.2107498).
8. 8)
  - 19. Patil, G.C., Qureshi, S.: ‘Asymmetric drain underlap dopant-segregated Schottky barrier ultrathin-body SOI MOSFET for low-power mixed-signal circuits’, Semicond. Sci. Technol., 2013, 28, (4), p. 045002 (doi: 10.1088/0268-1242/28/4/045002).
9. 9)
  - 8. Patil, G.C., Bonge, V.H., Malode, M.M., et al: ‘Novel δ-doped partially insulated junctionless transistor for mixed signal integrated circuits’, Superlattices Microstruct., 2016, 90, pp. 247–256 (doi: 10.1016/j.spmi.2015.12.024).
10. 10)
  - 15. Sun, J.J., Dou, W., Zhou, B., et al: ‘Junctionless in-plane-gate transparent thin-film transistors’, Appl. Phys. Lett., 2011, 99, p. 193502 (doi: 10.1063/1.3659478).
11. 11)
  - 12. Lee, C.-W., Nazarov, A.N., Ferain, I., et al: ‘Low subthreshold slope in junctionless multigate transistors’, Appl. Phys. Lett., 2010, 96, p. 102106 (doi: 10.1063/1.3358131).
12. 12)
  - 19. Sankapal, B.R., Lux-Steiner, M.C., Ennaoui, A.: ‘Synthesis and characterization of anatase-TiO2 thin films’, Appl. Surf. Sci., 2005, 239, pp. 165–170 (doi: 10.1016/j.apsusc.2004.05.142).
13. 13)
  - 16. Zhang, G., Wan, Q., Sun, J., et al: ‘Transparent junctionless thin-film transistors with tunable operation mode’, IEEE Electron Device Lett., 2013, 34, pp. 265–267 (doi: 10.1109/LED.2012.2232277).
14. 14)
  - 21. Majumder, S., Baviskar, P.K., Sankapal, B.R.: ‘Straightening of chemically deposited CdS nanowires through annealing towards improved PV device performance’, Ceram. Int., 2016, 42, pp. 6682–6091 (doi: 10.1016/j.ceramint.2016.01.027).
15. 15)
  - 1. Colinge, P.J., Lee, W.C., Afzalian, A., et al: ‘Nanowire transistors without junctions’, Nat. Nanotechnol., 2010, 5, pp. 225–229 (doi: 10.1038/nnano.2010.15).
16. 16)
  - 3. Abadi, R.M.I., Saremi, M.: ‘A resonant tunneling nanowire field effect transistor with physical contractions: a negative differential resistance device for low power very large scale integration applications’, J. Electron. Mater., 2018, 47, pp. 1091–1098 (doi: 10.1007/s11664-017-5823-z).
17. 17)
  - 21. Imenabadi, R.M., Saremi, M., Vandenberghe, W.G.: ‘A novel PNPN-like Z-shaped tunnel field-effect transistor with improved ambipolar behavior and RF performance’, IEEE Trans. Electron Dev., 2017, 64, (11), pp. 4752–4758 (doi: 10.1109/TED.2017.2755507).
18. 18)
  - 20. Patil, G.C., Qureshi, S.: ‘A novel δ-doped partially insulated dopant-segregated Schottky barrier SOI MOSFET for analog/RF applications’, Semicond. Sci. Technol., 2011, 26, (8), p. 085002 (doi: 10.1088/0268-1242/26/8/085002).
19. 19)
  - 5. Patil, G.C., Qureshi, S.: ‘Underlap channel metal source/drain SOI MOSFET for thermally efficient low-power mixed signal circuits’, Microelectron. J., 2012, 43, pp. 321–328 (doi: 10.1016/j.mejo.2011.12.015).
20. 20)
  - 17. Mejia, I., Heredia, G.G., Villasenor, A.L.S., et al: ‘Solution-based CdS on HfO2 thin films for high-gain and low-voltage unipolar inverters’, IEEE Trans. Electron Devices, 2016, 63, pp. 1437–1443 (doi: 10.1109/TED.2016.2532803).
21. 21)
  - 18. Koprek, A., Mirédin, O.C., Wuerz, R., et al: ‘Cd and impurity redistribution at the CdS/CIGS interface after annealing of CIGS-based solar cells resolved by atom probe tomography’, IEEE J. Photovoltaics, 2017, 7, pp. 313–321 (doi: 10.1109/JPHOTOV.2016.2629841).
22. 22)
  - 29. Choi, S.J., Moon, D.I., Kim, S., et al: ‘Sensitivity of threshold voltage to nanowire width variation in junctionless transistors’, IEEE Electron Device Lett., 2011, 32, (2), pp. 125–127 (doi: 10.1109/LED.2010.2093506).

Approach for fabricating JLT using chemically deposited cadmium sulphide and titanium dioxide

References

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