© The Institution of Engineering and Technology
In this work, a distinctive approach for the suppression of ambipolar behaviour of novel polarity control electrically doped hetero tunnel field effect transistor (TFET) has been reported. For this purpose, a wider band gap material, gallium arsenide phosphide has been employed at drain/channel regions. However, narrow band-gap material, silicon has been used in the source region. This combination of materials leads to a huge reduction in the ambipolar current and significant improvement in ON-state current due to the reduction in the electric field at the drain/channel interface and improvement in tunnelling rate at the source/channel interface, respectively. The proposed device also reduces the drain to source capacitance due to the presence of potential barrier width which leads to improvement in the radiofrequency performance. Therefore, the proposed device is very useful for ultralow power circuit applications. Moreover, polarity gates (PG1 and PG2) have been considered for the formation of n+ (drain) and p+ (source) regions. Hence, the proposed structure avoids ion implantation, random doping fluctuation, and high thermal budget unlike in the case of conventional TFETs, as the latter is physically doped. All the simulations have been performed using ATLAS software.
References
-
-
1)
-
2)
-
16. Anghel, C., Hraziia, A.G.: ‘30-nm tunnel FET with improved performance and reduce ambipolar current’, IEEE Trans. Electron Devices, 2011, 58, pp. 1649–1653 (doi: 10.1109/TED.2011.2128320).
-
3)
-
3. Boucart, K., Ionescu, A.M.: ‘Double-gate tunnel FET with high-k gate dielectric’, IEEE Trans. Electron Devices, 2007, 54, (7), pp. 1725–1733 (doi: 10.1109/TED.2007.899389).
-
4)
-
9. De Marchi, M., Sacchetto, D., Frache, S., et al: ‘Polarity control in double-gate, gate-All-around vertically stacked silicon nanowire FETs’. Proc. IEEE Electronic Device Meeting, San Francisco, CA, USA, 2012, pp. 841–844.
-
5)
-
3. Virani, H.G., Adari, R.B.R., Kottantharayil, A.: ‘Dualk spacer device architecture for the improvement of performance of silicon n channel tunnel FETs’, IEEE Trans. Electron Devices, 2010, 57, (10), pp. 2410–2417 (doi: 10.1109/TED.2010.2057195).
-
6)
-
2. Seabaugh, A.C., Zhang, Q.: ‘Low-voltage tunnel transistors for beyond CMOS logic’, Proc. IEEE, 2010, 98, (12), pp. 2095–110 (doi: 10.1109/JPROC.2010.2070470).
-
7)
-
14. Damrongplasit, N., Shin, C., Kim, S.H., et al: ‘Study of random dopant fluctuation effects in germanium-source tunnel FETs’, IEEE Trans. Electron Dev., 2011, 58, (10), pp. 3541–3548 (doi: 10.1109/TED.2011.2161990).
-
8)
-
24. Nigam, K., Kondekar, P., Sharma, D.: ‘DC characteristics and analog/RF performance of novel polarity control GaAs-Ge based tunnel field effect transistor’, Superlattices Microstruct., 2016, 92, pp. 224–231 (doi: 10.1016/j.spmi.2016.01.032).
-
9)
-
14. Chandan, B.V., Dasari, S., Yadav, S., et al: ‘Approach to suppress ambipolarity and improve RF and linearity performances on ED-tunnel FET’, IET Micro Nano Lett., 2018, 13, (5), pp. 684–689 (doi: 10.1049/mnl.2017.0814).
-
10)
-
16. Kondekar, P.N., Nigam, K., Pandey, S., et al: ‘Design and analysis of polarity controlled electrically doped tunnel FET with bandgap engineering for analog/RF applications’, IEEE Trans. Electron Devices, 2016, 64, (2), pp. 412–418 (doi: 10.1109/TED.2016.2637638).
-
11)
-
23. Nigam, K., Pandey, S., Kondekar, P.N., et al: ‘A barrier controlled charge plasma-based TFET with gate engineering for ambipolar suppression and RF/linearity performance improvement’, IEEE Trans. Electron Devices, 2017, 64, (6), pp. 2751–2757 (doi: 10.1109/TED.2017.2693679).
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