http://iet.metastore.ingenta.com
1887

Approach to suppress the ambipolar current conduction and improve radiofrequency performance in polarity control electrically doped hetero TFET

Approach to suppress the ambipolar current conduction and improve radiofrequency performance in polarity control electrically doped hetero TFET

For access to this article, please select a purchase option:

Buy article PDF
$19.95
(plus tax if applicable)
Buy Knowledge Pack
10 articles for $120.00
(plus taxes if applicable)

IET members benefit from discounts to all IET publications and free access to E&T Magazine. If you are an IET member, log in to your account and the discounts will automatically be applied.

Learn more about IET membership 

Recommend Title Publication to library

You must fill out fields marked with: *

Librarian details
Name:*
Email:*
Your details
Name:*
Email:*
Department:*
Why are you recommending this title?
Select reason:
 
 
 
 
 
Micro & Nano Letters — Recommend this title to your library

Thank you

Your recommendation has been sent to your librarian.

In this work, a distinctive approach for the suppression of ambipolar behaviour of novel polarity control electrically doped hetero tunnel field effect transistor (TFET) has been reported. For this purpose, a wider band gap material, gallium arsenide phosphide has been employed at drain/channel regions. However, narrow band-gap material, silicon has been used in the source region. This combination of materials leads to a huge reduction in the ambipolar current and significant improvement in ON-state current due to the reduction in the electric field at the drain/channel interface and improvement in tunnelling rate at the source/channel interface, respectively. The proposed device also reduces the drain to source capacitance due to the presence of potential barrier width which leads to improvement in the radiofrequency performance. Therefore, the proposed device is very useful for ultralow power circuit applications. Moreover, polarity gates (PG1 and PG2) have been considered for the formation of n+ (drain) and p+ (source) regions. Hence, the proposed structure avoids ion implantation, random doping fluctuation, and high thermal budget unlike in the case of conventional TFETs, as the latter is physically doped. All the simulations have been performed using ATLAS software.

References

    1. 1)
    2. 2)
    3. 3)
    4. 4)
    5. 5)
    6. 6)
    7. 7)
    8. 8)
    9. 9)
      • 9. De Marchi, M., Sacchetto, D., Frache, S., et al: ‘Polarity control in double-gate, gate-All-around vertically stacked silicon nanowire FETs’. Proc. IEEE Electronic Device Meeting, San Francisco, CA, USA, 2012, pp. 841844.
    10. 10)
      • 10. ATLAS Device Simulation Software, Silvaco Int., Santa Clara, CA, 2015.
    11. 11)
http://iet.metastore.ingenta.com/content/journals/10.1049/mnl.2018.5598
Loading

Related content

content/journals/10.1049/mnl.2018.5598
pub_keyword,iet_inspecKeyword,pub_concept
6
6
Loading
This is a required field
Please enter a valid email address