PSJ LDMOS with a VK dielectric layer

PSJ LDMOS with a VK dielectric layer

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A partial super junction lateral double-diffused metal–oxide–semiconductor field-effect transistor with a variable-k dielectric layer (PSJ VK LDMOS) is proposed in this Letter. Low-k material and PSJ are introduced into the device. PSJ provides a low-resistance channel to reduce the specific on-resistance (R on,sp). Furthermore, according to an enhanced dielectric layer field, low-k buried layer can sustain the high breakdown voltage (BV). To eliminate substrate-assisted depletion effect and improve the lateral BV of the proposed structure, the charge compensation layer in the device adopts a variation of lateral doping technique and is combined with the N pillar in PSJ. Ultimately, the simulation results show that BV of 795.5 V and the figure of merit (FOM) of 6.1 MW cm−2 are achieved for PSJ VK LDMOS. BV and FOM are enhanced by 71.4 and 81.1%, respectively, compared with con. PSJ SOI LDMOS with the drift region length of 46.5 μm. Furthermore, R on,sp of 103.4 mΩ cm2 is reduced by 31.2% compared with the ‘silicon limit’ at the same BV class, which breaks the ‘silicon limit’.


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