The impact of high-k dielectric pocket (DP) on the ambipolar conduction of tunnel field-effect transistors (TFETs) is demonstrated using two-dimensional Technology Computer Aided Design (TCAD) simulations. In the proposed structure of TFETs, an optimised portion of the upper drain region is replaced with a high-k DP at the channel–drain interface. It is demonstrated that due to the enhancement of the depleted drain region under DP, the minimum tunnelling width at channel–drain interface increases, and attains a maximum value for an optimum length and thickness of DP. Eventually, this increment in the minimum tunnelling width leads to a significant reduction in ambipolar conduction in TFETs. Furthermore, it is shown that performance parameters including the ON-state current, subthreshold swing and output characteristics are not affected by the presence of the proposed DP. Even, the gate-to-drain capacitance is reduced with the inclusion of DP at the channel–drain interface, thus leading to an improved cut-off frequency of TFETs. Moreover, it is also demonstrated that only a 10 nm of gate-on-drain overlapping along with this DP is capable of eliminating the ambipolarity completely for even a higher gate voltage of −0.8 V.