http://iet.metastore.ingenta.com
1887

Split-gate LDMOS with double vertical field plates

Split-gate LDMOS with double vertical field plates

For access to this article, please select a purchase option:

Buy article PDF
£12.50
(plus tax if applicable)
Buy Knowledge Pack
10 articles for £75.00
(plus taxes if applicable)

IET members benefit from discounts to all IET publications and free access to E&T Magazine. If you are an IET member, log in to your account and the discounts will automatically be applied.

Learn more about IET membership 

Recommend Title Publication to library

You must fill out fields marked with: *

Librarian details
Name:*
Email:*
Your details
Name:*
Email:*
Department:*
Why are you recommending this title?
Select reason:
 
 
 
 
 
Micro & Nano Letters — Recommend this title to your library

Thank you

Your recommendation has been sent to your librarian.

In this study, a novel split-gate lateral double-diffused metal oxide semiconductor field effect transistor with double vertical field plates (SG DVFP LDMOS) is proposed. The first feature of the SG DVFP LDMOS is that the SG with gradient gate oxide is introduced. The SG not only optimises the bulk electric field distributions to increase the breakdown voltage (BV) but also reduces the gate-drain charge (Q GD) owing to the thick gate oxide. The second feature of the SG DVFP LDMOS is the presence of the DVFP and P-pillar. They modulate the bulk electric field distributions and assist to deplete the drift region. So the specific on-resistance (R on,sp) is decreased and the BV is improved. The source vertical field plate reduces the contact region between the gate and drain, thereby the Q GD is reduced. Compared with the conventional SG LDMOS and rectangle-gate DVFP LDMOS, the figure of merit FOM1 of SG DVFP LDMOS is increased by 123.2 and 86.6%, and the loss figure of merit FOM2 is enhanced to 16.9 and 37.2%. Simultaneously, the key process steps of the SG DVFP LDMOS are proposed.

References

    1. 1)
    2. 2)
    3. 3)
    4. 4)
      • 4. Fan, J., Zou, Y., Wang, H., et al: ‘A novel structure of SOI lateral MOSFET with vertical field plate’. Proc. IEEE Int. Conf. on Optoelectronics and Microelectronics, Changchun, China, 2015, pp. 360364.
    5. 5)
    6. 6)
    7. 7)
    8. 8)
      • 8. Zhang, W., Qiao, M., Wu, L., et al: ‘Ultra-low specific on-resistance SOI high voltage trench LDMOS with dielectric field enhancement based on ENBULF concept’. Proc. IEEE of ISPSD, Kanazawa, Japan, 2013, pp. 329332.
    9. 9)
    10. 10)
    11. 11)
    12. 12)
    13. 13)
      • 13. Jiang, H., Wei, J., Dai, X., et al: ‘Silicon carbide split-gate MOSFET with merged Schottky barrier diode and reduced switching loss’. Proc. IEEE of ISPSD, Prague, 2016, pp. 5962.
    14. 14)
    15. 15)
    16. 16)
    17. 17)
    18. 18)
http://iet.metastore.ingenta.com/content/journals/10.1049/mnl.2018.5162
Loading

Related content

content/journals/10.1049/mnl.2018.5162
pub_keyword,iet_inspecKeyword,pub_concept
6
6
Loading
This is a required field
Please enter a valid email address