© The Institution of Engineering and Technology
This work investigates the delay performance of junctionless silicon nanotube (JLSiNT) field-effect transistor (FET) based 6T SRAM cell. The study demonstrates that the delay performance of symmetric drain/source DS-JLSiNT FET (inner gate covers drain, channel, and source regions) based 6T SRAM gets improved when the inner gate of nanotube covers only either drain and channel regions (D-JLSiNT FET) or source and channel regions (S-JLSiNT FET) because of improved I on/C gg. The improvement in read (write) access time is ∼22% (17%) and ∼9% (20%) when DS-JLSiNT FET is replaced by D-JLSiNT FET and S-JLSiNT FET, respectively, in DS-JLSiNT FET based 6T SRAM. Furthermore, due to partial covering of inner gate, the gate electrostatic integrity is reduced which decreases the ratio of on-current to off-current (I on/I off) resulting in degraded static noise margin (SNM). However, the deterioration in write SNM, hold SNM, and read SNM are almost minimal (∼0.3, 0.9, and 2%, respectively) for S-JLSiNT FET based SRAM as compared to DS-JLSiNT FET based SRAM. However, the deterioration in SNMs is aggravated for D-JLSiNT FET based SRAM as compared to DS-JLSiNT FET based SRAM. Thus, S-JLSiNT FET is the best configuration for designing of JLSiNT FET based 6T SRAM cell.
References
-
-
1)
-
22. Tayal, S., Nandi, A.: ‘Effect of FIBL in-conjunction with channel parameters on analog and RF FOM of FinFET’, Superlattices Microstruct., 2017, 105, pp. 152–162 (doi: 10.1016/j.spmi.2017.03.018).
-
2)
-
14. Lou, H., Zhang, L., Zhu, Y., et al: ‘A junctionless nanowire transistor with a dual-material gate’, IEEE Trans. Electron Devices, 2012, 59, (7), pp. 1829–1836 (doi: 10.1109/TED.2012.2192499).
-
3)
-
10. Tayal, S., Nandi, A.: ‘Analog/RF performance analysis of inner gate engineered junctionless Si nanotube’, Superlattices Microstruct., 2017, 111, pp. 862–871 (doi: 10.1016/j.spmi.2017.07.045).
-
4)
-
8. Fahad, H.M., Smith, C.E., Rojas, J.P., et al: ‘Silicon nanotube field effect transistor with core-shell gate stacks for enhanced high-performance operation and area scaling benefits’, Nano Lett.., 2011, 11, (10), pp. 4393–4399 (doi: 10.1021/nl202563s).
-
5)
-
6)
-
2. Nandi, A., Saxena, A.K., Dasgupta, S.: ‘Design and analysis of analog performance of dual-k spacer based underlap N/P-FinFET at 12 nm gate length’, IEEE Trans. Electron Devices, 2013, 60, (5), pp. 1529–1535 (doi: 10.1109/TED.2013.2250975).
-
7)
-
4. Wang, R., Zhuge, J., Huang, R., et al: ‘Analog/RF performance of Si nanowire MOSFETs and the impact of process variation’, IEEE Trans. Electron Devices, 2007, 54, (6), pp. 1288–1294 (doi: 10.1109/TED.2007.896598).
-
8)
-
6. Tekleab, D.: ‘Device performance of silicon nanotube field effect transistor’, IEEE Electon Device Lett., 2014, 35, (5), pp. 506–508 (doi: 10.1109/LED.2014.2310175).
-
9)
-
5. Tekleab, D., Tran, H.H., Slight, J.W.: ‘Silicon nanotube MOSFET’, .
-
10)
-
1. Colinge, P.J., Lee, W.C., Afzalian, A., et al: ‘Nanowire transistors without junctions’, Nat. Nanotechnol., 2010, 5, pp. 225–229 (doi: 10.1038/nnano.2010.15).
-
11)
-
14. Gnani, E., Gnudi, A., Reggiani, S., et al: ‘Theory of the junctionless nanowire FET’, IEEE Trans. Electron Devices, 2011, 58, (9), pp. 2903–2910 (doi: 10.1109/TED.2011.2159608).
-
12)
-
20. Cho, S., Lee, J.S., Kim, K.R., et al: ‘RF performance and small-signal parameter extraction of junctionless silicon nanowire MOSFETs’, IEEE Trans. Electron Devices, 2011, 58, pp. 1388–1396 (doi: 10.1109/TED.2011.2109724).
-
13)
-
22. Nandi, A., Saxena, A.K., Dasgupta, S.: ‘Enhancing low temperature analog performance of underlap FinFET at scaled gate lengths’, IEEE Trans. Electron Devices, 2014, 61, (11), pp. 3705–3709 (doi: 10.1109/TED.2014.2353139).
-
14)
-
24. Kaushal, G., Jeong, H., Maheshwaram, S., et al: ‘Low power SRAM design for 14 nm GAA Si-nanowiretechnology’, Microelectron. J., 2015, 46, pp. 1239–1247 (doi: 10.1016/j.mejo.2015.10.016).
-
15)
-
25. Huynh-Bao, T., Sakhare, S., Yakimets, D., et al: ‘A comprehensive benchmark and optimization of 5-nm lateral and vertical GAA 6T-SRAMs’ IEEE trans. Electron Devices, 2016, 63, (2), pp. 643–649 (doi: 10.1109/TED.2015.2504729).
-
16)
-
27. Saini, G., Choudhary, S.: ‘Improving the performance of SRAMs using asymmetric junctionless accumulation mode (JAM) FinFETs’, Microelectron. J., 2016, 58, pp. 1–8 (doi: 10.1016/j.mejo.2016.10.004).
-
17)
-
1. Kranti, A., Armstrong, G.A.: ‘Design and optimization of FinFETs for ultra-low-voltage analog application’, IEEE Trans. Electron Devices, 2011, 54, (6), pp. 3308–3315.
-
18)
-
12. Tayal, S., Nandi, A.: ‘Optimization of gate-stack in junctionless Si-nanotube FET for analog/RF applications’, Mater. Sci. Semicond. Process., 2018, 80, pp. 63–67 (doi: 10.1016/j.mssp.2018.02.014).
-
19)
-
15. Ambika, R., Srinivasan, R.: ‘Performance analysis of n-type junctionless silicon nanotube field effect transistor’, J. Nanoelectron. Optoelectron, 2016, 11, pp. 1–7 (doi: 10.1166/jno.2016.1899).
-
20)
-
7. Ambika, R., Srinivasan, R.: ‘Analysis of independent gate operation in Si nano tube FET and threshold prediction model using 3D numerical simulation’, J. Comput. Electron., 2016, 15, pp. 778–786 (doi: 10.1007/s10825-016-0822-5).
-
21)
-
13. Pal, P.K., Kaushik, B.K., Dasgupta, S.: ‘High-performance and robust SRAM cell based on asymmetric dual-k spacer FinFETs’, IEEE Trans. Electron Devices, 2013, 60, (10), pp. 3371–3377 (doi: 10.1109/TED.2013.2278201).
-
22)
-
27. Pratap, Y., Haldar, S., Gupta, R.S., et al: ‘Performance evaluation and reliability issues of junctionless CSG MOSFET for RFIC design’, IEEE Trans. Device Mater. Reliab., 2014, 14, pp. 418–425 (doi: 10.1109/TDMR.2013.2296524).
-
23)
-
9. Ghosh, D., Parihar, M.S., Armstrong, G.A., et al: ‘High-performance junctionless MOSFETs for ultralow-power analog/RF applications’, IEEE Electron Device Lett., 2012, 33, (10), pp. 1477–1479 (doi: 10.1109/LED.2012.2210535).
-
24)
-
18. Jayakumar, G.D., Srinivasan, R.: ‘Silicon nanotube SRAM and its SEU reliability’, Superlattices Microstruct., 2017, 106, pp. 129–138 (doi: 10.1016/j.spmi.2017.03.057).
-
25)
-
16. Sahay, S., Kumar, M.J.: ‘Nanotube junctionless FET: proposal, design, and investigation’, IEEE Trans. Electron Devices, 2017, 64, (4), pp. 1851–1856 (doi: 10.1109/TED.2017.2672203).
http://iet.metastore.ingenta.com/content/journals/10.1049/mnl.2017.0867
Related content
content/journals/10.1049/mnl.2017.0867
pub_keyword,iet_inspecKeyword,pub_concept
6
6