access icon free Enhancing the delay performance of junctionless silicon nanotube based 6T SRAM

This work investigates the delay performance of junctionless silicon nanotube (JLSiNT) field-effect transistor (FET) based 6T SRAM cell. The study demonstrates that the delay performance of symmetric drain/source DS-JLSiNT FET (inner gate covers drain, channel, and source regions) based 6T SRAM gets improved when the inner gate of nanotube covers only either drain and channel regions (D-JLSiNT FET) or source and channel regions (S-JLSiNT FET) because of improved I on/C gg. The improvement in read (write) access time is ∼22% (17%) and ∼9% (20%) when DS-JLSiNT FET is replaced by D-JLSiNT FET and S-JLSiNT FET, respectively, in DS-JLSiNT FET based 6T SRAM. Furthermore, due to partial covering of inner gate, the gate electrostatic integrity is reduced which decreases the ratio of on-current to off-current (I on/I off) resulting in degraded static noise margin (SNM). However, the deterioration in write SNM, hold SNM, and read SNM are almost minimal (∼0.3, 0.9, and 2%, respectively) for S-JLSiNT FET based SRAM as compared to DS-JLSiNT FET based SRAM. However, the deterioration in SNMs is aggravated for D-JLSiNT FET based SRAM as compared to DS-JLSiNT FET based SRAM. Thus, S-JLSiNT FET is the best configuration for designing of JLSiNT FET based 6T SRAM cell.

Inspec keywords: SRAM chips; nanotube devices; field effect transistor circuits; elemental semiconductors; silicon; integrated circuit noise; delays

Other keywords: channel regions; static noise margin; gate electrostatic integrity; junctionless silicon nanotube field-effect transistor based 6T SRAM; symmetric drain-source-JLSiNT FET; SNM; Si; delay performance enhancement; DS-JLSiNT FET

Subjects: Memory circuits; Semiconductor storage

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http://iet.metastore.ingenta.com/content/journals/10.1049/mnl.2017.0867
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