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access icon free Degradation induced by hot carrier and cold carrier in 65-nm NMOSFETs with enclosed gate and two-edged gate layouts

© The Institution of Engineering and Technology
Received 28/11/2017, Accepted 23/04/2018, Revised 13/03/2018, Published 01/08/2018

In this work, performance degradation of 65 nm N-channel metal-oxide-semiconductor field effect transistors (NMOSFETs) with enclosed gate and two-edged gate layouts under hot carrier stress and constant voltage stress is investigated. Compared with the cold carrier, the hot carrier effect (HCE) causes more serious degradation in threshold voltage and transconductance. It is shown that cold carrier contribution is reversible, while HCE damage is permanent, it cannot be reversed by application of the annealing bias. Meanwhile, an enclosed gate NMOSFET is proved to have higher resistance to HCE than two-edged gate NMOSFET fabricated in the same 65 nm complementary metal-oxide-semiconductor (CMOS) technology according to the results of experiments. That is, the enclosed gate NMOSFET not only provides total-dose radiation tolerance but also improves the hot carrier reliability of advanced CMOS circuits. The contributions of the two types of carriers to the degradation of transistor performance are analysed. The physical mechanism of HCE reliability of different geometry MOSFETs is studied.

Inspec keywords: semiconductor device reliability; hot carriers; radiation hardening (electronics); MOSFET circuits; annealing; CMOS integrated circuits

Other keywords: HCE damage; enclosed gate NMOSFET; hot carrier stress; total-dose radiation tolerance; constant voltage stress; two-edged gate layouts; two-edged gate NMOSFET; CMOS circuits; NMOSFET; annealing bias; complementary metal-oxide-semiconductor technology; cold carrier contribution; size 65.0 nm; N-channel metal-oxide-semiconductor field effect transistors; CMOS technology; hot carrier reliability; enclosed gate layouts

Subjects: Insulated gate field effect transistors; Radiation effects (semiconductor technology); Reliability; CMOS integrated circuits; Annealing processes in semiconductor technology

References

    1. 1)
    2. 2)
      • 11. Li, E., Rosenbaum, E., Tao, J., et al: ‘Hot carrier effects in nMOSFETs in 0.1 μm CMOS technology’. Proc. Int. Reliability Physics Symp. (IRPS), San Diego, CA, USA, 1999, pp. 253–258.
    3. 3)
      • 12. Lu, Q., Takeuchi, H., Lin, R., et al: ‘Hot carrier reliability of n-MOSFET with ultra-thin HfO2 gate dielectric and poly-Si gate’. Proc. Int. Reliability Physics Symp. (IRPS), Dallas, TX, USA, 2002, pp. 429–430.
    4. 4)
      • 5. Xue, F., Wei, L., Ping, L., et al: ‘Total ionizing dose effects on n-channel metal oxide semiconductor transistors with annular-gate and ring-gate layouts’, Acta Phys. Sin., 2012, 61, (1), p. 016106.
    5. 5)
    6. 6)
    7. 7)
    8. 8)
      • 6. Mclain, M.L., Barnaby, H.J, Esqueda, I.S., et al: ‘Reliability of high performance standard two-edge and radiation hardened by design enclosed geometry transistors’. Proc. Int. Reliability Physics Symp. (IRPS), Montreal, Canada, 2009, pp. 174–179.
    9. 9)
      • 15. Leblebici, Y., Kang, S.: ‘Hot-carrier reliability of MOS VLSI circuits’ (Kluwer Academic Publisher, Norwell, MA, 1993).
    10. 10)
    11. 11)
    12. 12)
    13. 13)
    14. 14)
    15. 15)
    16. 16)
      • 14. Takeda, E., Yang, C., Miura-Hamada, A.: ‘Hot-carrier effects in MOS devices’ (Academic Press, Inc., San Diego, 1995).
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