© The Institution of Engineering and Technology
Tunnel field-effect transistor (TFET) is considered to have superior device performance compared with DG-metal–oxide–semiconductor FET in terms of reduced off-state current and lower subthreshold swing. However, performance of a device solely depends on the accuracy in the fabrication process. This work presents a systematic methodology in small-signal-radio-frequency (RF) and linearity domain to analyse the effect of variation in lateral straggle caused by the variation tilt angle during ion implantation process. From previously published researches, it is intuitively established fact that the accurate evaluation of intrinsic components and estimation of linearity in short channel devices is crucial to access the range of application of the device. In this work, the authors have investigated the RF intrinsic parameter performances of a silicon double gate TFET having variation in lateral straggle from 1 to 5 nm. This study includes the analysis of non-quasi-static RF bias-dependent parameters such as intrinsic capacitances (C gs, C gd), gate-to-drain intrinsic resistance (R gd) and intrinsic time delay (τ). Similarly, the device linearity and reliability are investigated here in terms of higher-order transconductances (gm 2 and gm 3), VIP2, VIP3, IMD3, IIP3 and 1 dB compression point.
References
-
-
1)
-
17. Yang, Y., Xin Tong, T., Yang, L.T., et al: ‘Tunneling field-effect transistor: capacitance components and modeling’, IEEE Electron Device Lett., 2010, 31, (7), pp. 752–754 (doi: 10.1109/LED.2010.2047240).
-
2)
-
33. Ghosh, P., Haldar, S., Gupta, R.S., et al: ‘An investigation of linearity performance and intermodulation distortion of GME CGT MOSFET for RFIC design’, IEEE Trans. Electron Devices, 2012, 59, (12), pp. 3263–3268 (doi: 10.1109/TED.2012.2219537).
-
3)
-
16. Kang, S., Choi, B., Kim, B.: ‘Linearity analysis of CMOS for RF application’, IEEE Trans. Microw. Theory Tech., 2003, 51, pp. 972–977 (doi: 10.1109/TMTT.2003.808709).
-
4)
-
9. Kranti, A., Armstrong, G.A.: ‘Design and optimization of FinFETs for ultra-low-voltage analog applications’, IEEE Trans. Electron Devices, 2007, 54, (12), pp. 3308–3316 (doi: 10.1109/TED.2007.908596).
-
5)
-
20. Cho, S., Lee, J.S., Kim, K.R., et al: ‘RF performance and small-signal parameter extraction of junctionless silicon nanowire MOSFETs’, IEEE Trans. Electron Devices, 2011, 58, pp. 1388–1396 (doi: 10.1109/TED.2011.2109724).
-
6)
-
14. Adan, A.O., Yoshimasu, T., Shitara, S., et al: ‘Linearity and low-noise performance of SOI MOSFETs for RF applications’, IEEE Trans. Electron Devices, 2002, 49, pp. 881–888 (doi: 10.1109/16.998598).
-
7)
-
27. Pratap, Y., Haldar, S., Gupta, R.S., et al: ‘Performance evaluation and reliability issues of junctionless CSG MOSFET for RFIC design’, IEEE Trans. Device Mater. Reliab., 2014, 14, pp. 418–425 (doi: 10.1109/TDMR.2013.2296524).
-
8)
-
1. Choi, W.Y., Park, B.G., Lee, J.D., Liu, T.J.K.: ‘Tunneling field-effect transistors (TFETs) with subthreshold swing (SS) less than 60 mV/dec’, IEEE Electron Device Lett., 2007, 28, (8), pp. 743–745 (doi: 10.1109/LED.2007.901273).
-
9)
-
6. Reddick, W.M., Amaratunga, G.A.J.: ‘Silicon surface tunnel transistor’, Appl. Phys. Lett., 1995, 67, pp. 494–496 (doi: 10.1063/1.114547).
-
10)
-
30. Rogers, J., Plett, C.: ‘Radio frequency integrated circuit design’ (Artech House, 2003), pp. 28–32.
-
11)
-
13. Ghosh, S., Koley, K., Sarkar, C.K.: ‘Impact of the lateral straggle on the analog and RF performance of TFET’, Microelectron. Reliab., 2015, 55, pp. 326–331 (doi: 10.1016/j.microrel.2014.10.008).
-
12)
-
25. Mallik, A., Chattopadhyay, A.: ‘Drain-dependence of tunnel fieldeffect transistor characteristics: the role of the channel’, IEEE Trans. Electron Dev., 2011, 58, (12), pp. 4250–4257 (doi: 10.1109/TED.2011.2169416).
-
13)
-
17. Sentaurus TCAD Manuals: ‘Release H-2013.03’ (Synopsys Inc., Mountain View, CA, USA, 2013).
-
14)
-
28. Niu, G., Liang, Q., Cressler, J.D., et al: ‘RF linearity characteristics of SiGe HBTs’, IEEE Trans. Microw. Theory Tech., 2001, 49, pp. 1558–1565 (doi: 10.1109/22.942567).
-
15)
-
18. Huang, Q., Huang, R., Zhan, Z., et al: ‘A novel Si tunnel FET with 36 mV/dec subthreshold slope based on junction’. Depleted-Modulation through Striped Gate Configuration, 2012 IEDM, pp. 8.5.1–8.5.4.
-
16)
-
6. Khatami, Y., Banerjee, K.: ‘Steep subthreshold slope n- and p-type tunnel-FET devices for low-power and energy-efficient digital circuits’, IEEE Trans. Electron Devices, 2009, 56, (11), pp. 2752–2761 (doi: 10.1109/TED.2009.2030831).
-
17)
-
10. Kranti, A., Armstrong, G.A.: ‘Design and operation of FinFETs for low-voltage analog applications’, IEEE Electron Device Lett., 2007, 28, pp. 139–141 (doi: 10.1109/LED.2006.889239).
-
18)
-
26. Woerlee, P.H., Knitel, M.J., Langevelde, R.V., et al: ‘RF-CMOS performance trends’, IEEE Trans. Electron Devices, 2001, 48, pp. 1776–1782 (doi: 10.1109/16.936707).
-
19)
-
19. Kang, I.M., Shin, H.: ‘Non-quasi-static small-signal modeling and analytical parameter extraction of SOI FinFETs’, IEEE Trans. Nanotechnol., 2006, 5, pp. 205–210 (doi: 10.1109/TNANO.2006.869946).
-
20)
-
4. Tsividis, Y.: ‘Operation and modeling of MOS transistor’ (McGraw-Hill, New York, 1999, 2nd edn.).
-
21)
-
30. Mallik, A., Chattopadhyay, A.: ‘Tunnel field-effect transistors for analog/mixed-signal system-on-chip applications’, IEEE Trans. Electron Devices, 2012, 59, (4), pp. 888–894 (doi: 10.1109/TED.2011.2181178).
-
22)
-
15. Kumar, S.P., Agrawal, A., Chaujar, R., et al: ‘Device linearity and intermodulation distortion comparison of dual material gate and conventional AlGaN/GaN high electron mobility transistor’, Microelectron. Reliab., 2011, 51, pp. 587–596 (doi: 10.1016/j.microrel.2010.09.033).
-
23)
-
15. Ma, W., Kaya, S., Asenov, A.: ‘Study of RF linearity in sub-50 nm MOSFETs using simulations’, J. Solid-State Electron, 2004, 2, pp. 347–352.
-
24)
-
21. Cho, S., Lee, J.S., Kim, K.R., et al: ‘Analyses on small-signal parameters and radio-frequency modeling of gate-all-around tunneling field-effect transistors’, IEEE Trans. Electron Devices, 2011, 58, pp. 4164–4171 (doi: 10.1109/TED.2011.2167335).
-
25)
-
3. Boucart, K., Ionescu, A.M.: ‘Double-gate tunnel FET with high-k gate dielectric’, IEEE Trans. Electron Devices, 2007, 54, (7), pp. 1725–1733 (doi: 10.1109/TED.2007.899389).
-
26)
-
1. Dennard, R.H., Gaensslen, F.H., Rideout, V.L., et al: ‘Design of ion-implanted MOSFET's with very small physical dimensions’, IEEE J. Solid-State Circuits, 1974, 9, (5), pp. 256–268 (doi: 10.1109/JSSC.1974.1050511).
-
27)
-
29. Razavi, B.: ‘RF microelectronics’ (Prentice-Hall, NJ, 1998) .
-
28)
-
7. Chakraborty, S., Mallik, A., Sarkar, C.K., et al: ‘Impact of halo doping on the subthreshold performance of deep-sub micrometer CMOS devices and circuits for ultralow power analog/mixed signal applications’, IEEE Trans. Electron Devices, 2007, 54, (2), pp. 241–248 (doi: 10.1109/TED.2006.888630).
-
29)
-
3. Bhuwalka, K.K., Sedlmaier, S., Ludsteck, A.K., et al: ‘Vertical tunnel field-effect transistor’, IEEE Trans. Electron Devices, 2004, 51, pp. 279–282 (doi: 10.1109/TED.2003.821575).
-
30)
-
12. Kwong, M.Y., Kasnavi, R., Griffin, P., et al: ‘Impact of lateral source/drain abruptness on device performance’, IEEE Trans. Electron Devices, 2002, 49, pp. 1882–1890 (doi: 10.1109/TED.2002.806790).
http://iet.metastore.ingenta.com/content/journals/10.1049/mnl.2017.0326
Related content
content/journals/10.1049/mnl.2017.0326
pub_keyword,iet_inspecKeyword,pub_concept
6
6