Your browser does not support JavaScript!

Deep insight into linearity and NQS parameters of tunnel FET with emphasis on lateral straggle

Deep insight into linearity and NQS parameters of tunnel FET with emphasis on lateral straggle

For access to this article, please select a purchase option:

Buy article PDF
(plus tax if applicable)
Buy Knowledge Pack
10 articles for $120.00
(plus taxes if applicable)

IET members benefit from discounts to all IET publications and free access to E&T Magazine. If you are an IET member, log in to your account and the discounts will automatically be applied.

Learn more about IET membership 

Recommend Title Publication to library

You must fill out fields marked with: *

Librarian details
Your details
Why are you recommending this title?
Select reason:
Micro & Nano Letters — Recommend this title to your library

Thank you

Your recommendation has been sent to your librarian.

Tunnel field-effect transistor (TFET) is considered to have superior device performance compared with DG-metal–oxide–semiconductor FET in terms of reduced off-state current and lower subthreshold swing. However, performance of a device solely depends on the accuracy in the fabrication process. This work presents a systematic methodology in small-signal-radio-frequency (RF) and linearity domain to analyse the effect of variation in lateral straggle caused by the variation tilt angle during ion implantation process. From previously published researches, it is intuitively established fact that the accurate evaluation of intrinsic components and estimation of linearity in short channel devices is crucial to access the range of application of the device. In this work, the authors have investigated the RF intrinsic parameter performances of a silicon double gate TFET having variation in lateral straggle from 1 to 5 nm. This study includes the analysis of non-quasi-static RF bias-dependent parameters such as intrinsic capacitances (C gs, C gd), gate-to-drain intrinsic resistance (R gd) and intrinsic time delay (τ). Similarly, the device linearity and reliability are investigated here in terms of higher-order transconductances (gm 2 and gm 3), VIP2, VIP3, IMD3, IIP3 and 1 dB compression point.


    1. 1)
    2. 2)
    3. 3)
    4. 4)
    5. 5)
    6. 6)
    7. 7)
    8. 8)
    9. 9)
    10. 10)
      • 30. Rogers, J., Plett, C.: ‘Radio frequency integrated circuit design’ (Artech House, 2003), pp. 2832.
    11. 11)
    12. 12)
    13. 13)
      • 17. Sentaurus TCAD Manuals: ‘Release H-2013.03’ (Synopsys Inc., Mountain View, CA, USA, 2013).
    14. 14)
    15. 15)
      • 18. Huang, Q., Huang, R., Zhan, Z., et al: ‘A novel Si tunnel FET with 36 mV/dec subthreshold slope based on junction’. Depleted-Modulation through Striped Gate Configuration, 2012 IEDM, pp.
    16. 16)
    17. 17)
    18. 18)
    19. 19)
    20. 20)
      • 4. Tsividis, Y.: ‘Operation and modeling of MOS transistor’ (McGraw-Hill, New York, 1999, 2nd edn.).
    21. 21)
    22. 22)
    23. 23)
      • 15. Ma, W., Kaya, S., Asenov, A.: ‘Study of RF linearity in sub-50 nm MOSFETs using simulations’, J. Solid-State Electron, 2004, 2, pp. 347352.
    24. 24)
    25. 25)
    26. 26)
    27. 27)
      • 29. Razavi, B.: ‘RF microelectronics’ (Prentice-Hall, NJ, 1998) Chapter 2.
    28. 28)
    29. 29)
    30. 30)

Related content

This is a required field
Please enter a valid email address