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Junction-less charge plasma TFET with dual drain work functionality for suppressing ambipolar nature and improving radio-frequency performance

Junction-less charge plasma TFET with dual drain work functionality for suppressing ambipolar nature and improving radio-frequency performance

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This work deals with a distinct concept to realise the junction-less tunnel field effect transistor (JL TFET) by creating the plasma of charges. The crux of this study is to reduce ambipolar conduction and to improve high-frequency figure of merits. To construct a JL TFET, initially silicon film is considered and then metal electrodes are used to form drain and channel region. The drain electrode is separated into two sections and the work function of section adjacent to channel is selected higher than the other section. This provides a non-uniform doping profile in the drain region creating large barrier at the drain/channel junction to prevent the ambipolar conduction. Ambipolarity is reduced to from at . The selection of work function and length of drain electrode adjunct to channel is crucial for optimising device performance. This optimisation provides information that work function >4.0 eV and length = 10 nm completely suppresses the ambipolarity which is around with little degradation in ON-current. The high work function for the section of drain electrode adjunct to channel provides lower gate-to-drain capacitance () and superior high-frequency responses. Furthermore, performance assessment at circuit level is done by implementing primary digital circuits as inverter and NAND logic with lookup table based Verilog-A model.


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    19. 19)
      • 27. Chang, M.F., Yang, S.M., Chen, K.T.: ‘Wide VDD embedded asynchronous SRAM with dual-mode self-timed technique for dynamic voltage systems’, IEEE Trans. Circuits Syst. I, Regul. Pap., 2013, 56, pp. 2024.
    20. 20)
      • 19. Silvaco Int.: ‘ATLAS device simulation software’ (Santa Clara, CA, USA, 2014).
    21. 21)
    22. 22)
    23. 23)
    24. 24)
    25. 25)
    26. 26)
    27. 27)

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