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References
-
-
1)
-
3. Sahu, C., Singh, J.: ‘Charge-plasma based process variation immune junctionless transistor’, IEEE Electron Device Lett., 2014, 35, (3), pp. 411–413 (doi: 10.1109/LED.2013.2297451).
-
2)
-
7. Silvaco Int.: ‘ATLAS device simulation software’ (Santa Clara, CA, USA, 2014).
-
3)
-
4. Banerjee, S., Richardson, W., Coleman, J., et al: ‘A new three-terminal tunnel device’, IEEE Electron Device Lett.., 1987, 8, (8), pp. 347–349 (doi: 10.1109/EDL.1987.26655).
-
4)
-
8. Ghosh, B., Akram, M.W.: ‘Junctionless tunnel field effect transistor’, IEEE Electron Device Lett. , 2013, 34, (5), pp. 584–586 (doi: 10.1109/LED.2013.2253752).
-
5)
-
10. Jiang, X., Wang, R., Yu, T., et al: ‘Investigations on line-edge roughness (LER) and linewidth roughness (LWR) in nanoscale CMOS technology: Part II – Experimental results and impacts on device variability’, IEEE Trans. Electron Devices, 2013, 60, (11), pp. 3676–3682 (doi: 10.1109/TED.2013.2283517).
-
6)
-
3. Boucart, K., Ionescu, A.M.: ‘Double-gate tunnel FET with high-k gate dielectric’, IEEE Trans. Electron Devices, 2007, 54, (7), pp. 1725–1733 (doi: 10.1109/TED.2007.899389).
-
7)
-
1. Colinge, P.J., Lee, W.C., Afzalian, A., et al: ‘Nanowire transistors without junctions’, Nat. Nanotechnol., 2010, 5, pp. 225–229 (doi: 10.1038/nnano.2010.15).
-
8)
-
7. Kumar, M.J., Janardhanan, S.: ‘Doping-less tunnel field effect transistor: design and investigation’, IEEE Trans. Electron Devices, 2013, 60, (10), pp. 3285–3290 (doi: 10.1109/TED.2013.2276888).
-
9)
-
11. Pala, M.G., Esseni, D., Conzatti, F.: ‘Impact of interface traps on the IV curves of InAs tunnel-FETs and MOSFETs: a full quantum study’. Proc. IEEE IEDM, December 2012, pp. 1–4.
-
10)
-
6. De Marchi, M., Sacchetto, D., Frache, S., et al: ‘Polarity control in double-gate, gate-all-around vertically stacked silicon nanowire FETs’. Proc. IEEE Electron Devices Meeting (IEDM), December 2012, pp. 8.4.1–8.4.4.
-
11)
-
1. Leung, G., Chui, C.O.: ‘Variability impact of random dopant fluctuation on nanoscale junctionless FinFETs’, IEEE Electron Device Letts., 2012, 33, (6), pp. 767–769 (doi: 10.1109/LED.2012.2191931).
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