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Performance estimation of polarity controlled electrostatically doped tunnel field-effect transistor

Performance estimation of polarity controlled electrostatically doped tunnel field-effect transistor

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In this work, the performance estimation of polarity controlled electrostatically doped tunnel field-effect transistor (TFET) is reported. The proposed device exhibits heavily doped n-type Si-channel with two distinctive gates, namely control gate (CG) and polarity gate (PG). First, the CG and PG work functions of 4.72 eV are considered to convert the layer beneath CG and PG of intrinsic type. Next, the PG voltage of −1.2 V is used at source side to induce a p+ region, so that, it follows the similar trend as like a n +ip + gated structure of conventional TFET. Silvaco ATLAS simulation of the proposed device shows I ON/I OFF ratio of ∼7.8 × 1010 and OFF current is less than 1 fA, with high-k dielectric of gate material at V DS = 0.5, V. Finally, a minimum point subthreshold slope of 12 mV/decade at 300 K is achieved, which indicates that the proposed TFET has the potential to achieve better than ITRS low-standby-power switch performance.

References

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      • 6. De Marchi, M., Sacchetto, D., Frache, S., et al: ‘Polarity control in double-gate, gate-all-around vertically stacked silicon nanowire FETs’. Proc. IEEE Electron Devices Meeting (IEDM), December 2012, pp. 8.4.18.4.4.
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      • 7. Silvaco Int.: ‘ATLAS device simulation software’ (Santa Clara, CA, USA, 2014).
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      • 11. Pala, M.G., Esseni, D., Conzatti, F.: ‘Impact of interface traps on the IV curves of InAs tunnel-FETs and MOSFETs: a full quantum study’. Proc. IEEE IEDM, December 2012, pp. 14.
http://iet.metastore.ingenta.com/content/journals/10.1049/mnl.2016.0729
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