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RS flip-flop implementation based on all spin logic devices

RS flip-flop implementation based on all spin logic devices

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All spin logic (ASL) device is one of the promising post-CMOS candidates. Owing to unique features such as non-volatility, simple configuration, ultra-low-switching energy, and good scalability, ASL devices can be exploited in logic applications. Based on the characteristics of non-volatility and bistable states of ASL device, an RS flip-flop is proposed which is composed of seven ASL devices and employs a complementary clock signal scheme. Using the coupled spin-transport/magneto-dynamics model, validity of its logic operation is demonstrated. As a fundamental building block of sequential logic circuits, the proposed RS flip-flop will be an useful component for designing large-scale ASL sequential logic circuits.

References

    1. 1)
    2. 2)
    3. 3)
    4. 4)
    5. 5)
    6. 6)
    7. 7)
    8. 8)
    9. 9)
    10. 10)
    11. 11)
    12. 12)
    13. 13)
      • 13. Wang, S., Cai, L., Cui, H.Q., et al: ‘Switching Characteristics of all spin logic devices based on Co and Permalloy nanomagnet’, Acta Phys. Sin., 2016, 65, (9), pp. 110.
    14. 14)
    15. 15)
    16. 16)
    17. 17)
    18. 18)
      • 18. Augustine, C., Panagopoulos, G., Behin-Aein, B., et al: ‘Low-power functionality enhanced computation architecture using spin-based devices’. IEEE/ACM Int. Symp. on Nanoscale Architectures, 2011, pp. 129136.
    19. 19)
    20. 20)
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