RS flip-flop implementation based on all spin logic devices

RS flip-flop implementation based on all spin logic devices

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All spin logic (ASL) device is one of the promising post-CMOS candidates. Owing to unique features such as non-volatility, simple configuration, ultra-low-switching energy, and good scalability, ASL devices can be exploited in logic applications. Based on the characteristics of non-volatility and bistable states of ASL device, an RS flip-flop is proposed which is composed of seven ASL devices and employs a complementary clock signal scheme. Using the coupled spin-transport/magneto-dynamics model, validity of its logic operation is demonstrated. As a fundamental building block of sequential logic circuits, the proposed RS flip-flop will be an useful component for designing large-scale ASL sequential logic circuits.


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