Performance enhancement of asymmetrical underlap 3D-cylindrical GAA-TFET with low spacer width

Performance enhancement of asymmetrical underlap 3D-cylindrical GAA-TFET with low spacer width

For access to this article, please select a purchase option:

Buy article PDF
(plus tax if applicable)
Buy Knowledge Pack
10 articles for $120.00
(plus taxes if applicable)

IET members benefit from discounts to all IET publications and free access to E&T Magazine. If you are an IET member, log in to your account and the discounts will automatically be applied.

Learn more about IET membership 

Recommend Title Publication to library

You must fill out fields marked with: *

Librarian details
Your details
Why are you recommending this title?
Select reason:
Micro & Nano Letters — Recommend this title to your library

Thank you

Your recommendation has been sent to your librarian.

A comparative study of cylindrical gate-all-around (Cyl-GAA) tunnel field effect transistor (TFET) based on underlaps with varying spacer width is presented. Extensively, simulation results show that asymmetrical underlap (AU) GAA-TFET with low spacer width enhances the fringing field within the spacer. The proposed device structure has high I ON (6.9 × 10−4 A/µm), low I OFF (2.5 × 10−17 A/µm), and an enhanced I ON/I OFF (1013). This is due to the high series resistance at drain channel junction caused by AU. Furthermore, the proposed structure exhibits a steeper subthreshold swing (30 mV/dec) when compared with symmetrical underlap (SU) Cyl-GAA-TFET.


    1. 1)
    2. 2)
    3. 3)
      • 3. Lee, J.S., Choi, Y., Kang, M.: ‘Characteristics of gate-all-around hetero-gate-dielectric tunneling field-effect transistors’, Jpn. J. Appl. Phys., 2012, 51, pp. 06FE03-106FE03-5.
    4. 4)
    5. 5)
    6. 6)
    7. 7)
    8. 8)
    9. 9)
    10. 10)
    11. 11)
    12. 12)
    13. 13)
      • 13. Version E-2015, Synopsys, Inc., Mountain View, CA, USA, September 2015.
    14. 14)
    15. 15)
    16. 16)
      • 16. Versulst, A.S., Vandenberghe, W.G., Maex, K., et al: ‘Tunnel field-effect transistor without gate-drain overderlap’, Appl. Phys. Lett., 2007, 91, (5), pp. 053102-1053102-3.

Related content

This is a required field
Please enter a valid email address