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Performance enhancement of asymmetrical underlap 3D-cylindrical GAA-TFET with low spacer width

Performance enhancement of asymmetrical underlap 3D-cylindrical GAA-TFET with low spacer width

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A comparative study of cylindrical gate-all-around (Cyl-GAA) tunnel field effect transistor (TFET) based on underlaps with varying spacer width is presented. Extensively, simulation results show that asymmetrical underlap (AU) GAA-TFET with low spacer width enhances the fringing field within the spacer. The proposed device structure has high I ON (6.9 × 10−4 A/µm), low I OFF (2.5 × 10−17 A/µm), and an enhanced I ON/I OFF (1013). This is due to the high series resistance at drain channel junction caused by AU. Furthermore, the proposed structure exhibits a steeper subthreshold swing (30 mV/dec) when compared with symmetrical underlap (SU) Cyl-GAA-TFET.

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http://iet.metastore.ingenta.com/content/journals/10.1049/mnl.2016.0202
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