An ultrathin-channel trench single gate tunnelling field-effect transistor (trench SG-TFET) with a 5 nm channel thickness is proposed and investigated. Trench SG-TFETs demonstrate a higher I _ON (∼8 times), a steeper sub-threshold swing (SS) (average SS of 46.2 mV/decade and point SS of 21.8 mV/decade), and a higher I _ON/I _OFF current ratio (∼10 times) as compared with the conventional SG-TFET at V _DS = 0.4 V and temperature of 300 K. Also by using intrinsic region in drain, it has a strong immunity to short-channel effects in extremely scaled trench SG-TFETs. The proposed trench SG-TFET seems to be attractive for future energy-efficient circuit applications.

References

1. 1)
  - 6. Leonelli, D., Vandooren, A., Rooyackers, R., et al: ‘Multiple-gate tunneling field effect transistors with sub-60 mV/dec subthreshold slope’. Technical Digest SSDM, 2009, pp. 767–768.
2. 2)
  - 6. Appenzeller, J., Lin, Y.M., Knoch, J., et al: ‘Band-to-band tunneling in carbon nanotube field-effect transistors’, Phys. Rev. Lett., 2004, 93, (19), pp. 805–809 (doi: 10.1103/PhysRevLett.93.196805).
3. 3)
  - 15. ATLAS Device Simulation Software, Silvaco, Version 5.19.20R, 2014.
4. 4)
  - 19. Abdi, D.B., Jagadesh Kumar, M.: ‘PNPN tunnel FET with controllable drain side tunnel barrier width: proposal and analysis’, Superlattices Microstruct., 2015, 86, pp. 121–125 (doi: 10.1016/j.spmi.2015.07.045).
5. 5)
  - 9. Bardon, M.G., Neves, H.P., Puers, R., et al: ‘Pseudo-two dimensional model for double-gate tunnel FETs considering the junctions depletion regions’, IEEE Trans. Electron Devices, 2010, 57, (4), pp. 827–834 (doi: 10.1109/TED.2010.2040661).
6. 6)
  - 16. Abdi, D.B., Kumar, M.J.: ‘In-built N+ pocket p-n-p-n tunnel field-effect transistor’, IEEE Electron Device Lett., 2014, 35, (12), pp. 1170–1172 (doi: 10.1109/LED.2014.2362926).
7. 7)
  - 7. Kazazis, D., Jannaty, P., Zaslavsky, A., et al: ‘Tunneling field-effect transistor with epitaxial junction in thin germanium-on-insulator’, Appl. Phys. Lett., 2009, 94, (26), pp. 263508-1–263508-3 (doi: 10.1063/1.3168646).
8. 8)
  - 8. Ghosh, B., Akram, M.W.: ‘Junctionless tunnel field effect transistor’, IEEE Electron Device Lett. , 2013, 34, (5), pp. 584–586 (doi: 10.1109/LED.2013.2253752).
9. 9)
  - 11. Shih, C.-H., Chien, N.D.: ‘Physical operation and device design of short-channel tunnel field-effect transistors with graded silicon–germanium heterojunctions’, J. Appl. Phys., 2013, 113, (13), pp. 134507-1–134507-7 (doi: 10.1063/1.4795777).
10. 10)
  - 1. Choi, W.Y., Park, B.G., Lee, J.D., Liu, T.J.K.: ‘Tunneling field-effect transistors (TFETs) with subthreshold swing (SS) less than 60 mV/dec’, IEEE Electron Device Lett., 2007, 28, (8), pp. 743–745 (doi: 10.1109/LED.2007.901273).
11. 11)
  - 18. Ram, M.S., Abdi, D.B.: ‘Single grain boundary tunnel field effect transistors on recrystallized polycrystalline silicon: proposal and investigation’, IEEE Electron Device Lett., 2014, 35, (10), pp. 989–991 (doi: 10.1109/LED.2014.2351260).
12. 12)
  - 2. Bhuwalka, K.K., Schulze, J., Eisele, I.: ‘Performance enhancement of vertical tunnel field-effect transistor with SiGe in the layer’, Jpn. J. Appl. Phys., 2004, 43, (7A), pp. 4073–4078 (doi: 10.1143/JJAP.43.4073).
13. 13)
  - 3. Toh, E.-H., Wang, G.H., Chan, L., et al: ‘Device design and scalability of a double-gate tunneling field-effect transistor with silicon–germanium source’, Jpn. J. Appl. Phys., 2008, 47, (4), pp. 2593–2597 (doi: 10.1143/JJAP.47.2593).
14. 14)
  - 12. Chien, N.D., Shih, C.-H.: ‘Short-channel effect and device design of extremely scaled tunnel field-effect transistors’, Microelectron. Reliab., 2015, 55, (1), pp. 31–37 (doi: 10.1016/j.microrel.2014.09.028).
15. 15)
  - 5. Bhuwalka, K., Born, M., Schindler, M., et al: ‘P-channel tunnel field-effect transistors down to sub-50 nm channel lengths’, Jpn. J. Appl. Phys., 2006, 45, (4B), pp. 3106–3109 (doi: 10.1143/JJAP.45.3106).
16. 16)
  - 10. Shih, C.H., Chien, N.D.: ‘Sub-10 nm tunnel field-effect transistor with graded Si/Ge heterojunction’, IEEE Electron Device Lett., 2011, 32, (11), pp. 1498–1500 (doi: 10.1109/LED.2011.2164512).
17. 17)
  - 3. Boucart, K., Ionescu, A.M.: ‘Double-gate tunnel FET with high-k gate dielectric’, IEEE Trans. Electron Devices, 2007, 54, (7), pp. 1725–1733 (doi: 10.1109/TED.2007.899389).
18. 18)
  - 1. Kim, H.W., Kim, J.H., Kim, S.W., et al: ‘Tunneling field-effect transistor with Si/SiGe material for high current drivability’, Jpn. J. Appl. Phys., 2014, 53, (6), p. 06JE12-1–4 (doi: 10.7567/JJAP.53.062101).
19. 19)
  - 15. Schlosser, M., Bhuwalka, K.K., Sauter, M., et al: ‘Fringing-induced drain current improvement in the tunnel field-effect transistor with high-k gate dielectrics’, IEEE Trans. Electron Devices, 2009, 56, (1), pp. 100–108 (doi: 10.1109/TED.2008.2008375).
20. 20)
  - 8. Nayfeh, O.M., Hoyt, J.L., Antoniadis, D.: ‘Strained-band-to-band tunneling transistors: impact of tunnel-junction germanium composition and doping concentration on switching behavior’, IEEE Trans. Electron Devices, 2009, 56, (10), pp. 2264–2269 (doi: 10.1109/TED.2009.2028055).
21. 21)
  - 13. Ai, Y., Fan, J., Huang, R., et al: ‘Manufacturing method of envelope gate silicon nanometer diode with air side wall’. WO Patent No. 2012, 159314, A1, 29 November 2012.

Ultrathin-body tunnelling FET using a trench structure

References

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