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High-accuracy silicon-on-insulator accelerometer with an increased yield rate

High-accuracy silicon-on-insulator accelerometer with an increased yield rate

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This Letter presents a high accuracy silicon-on-insulator (SOI) capacitive accelerometer using a backside dry release process. To increase the yield rate of the process, the deep reactive iron etching (DRIE) process was improved using a grooved accompany wafer to balance the pressure inside the back cavity of the SOI devices. By using this method, almost all the devices after the DRIE will not crack. Thus, the yield rate is significantly increased. Furthermore, the DRIE process was improved by dividing the DRIE process into four stages to decrease the tilt angle of DRIE. It is experimentally demonstrated that the tilt angle of the side wall was decreased from 0.81° to 0.27° and the loss of the capacitive sensitivity caused by the error was decreased from 28 to 8%. Test results show that sensitivity, bias stability, and noise floor of the accelerometer is 3.1 V/g, 16 μg, and 3.1 μg/√Hz, respectively.

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      • 7. Li, P.C., Li, X.Y., Li, E.F., et al: ‘Design and fabrication of an in-plane SOI MEMS accelerometer with a high yield rate’. Tenth IEEE Int. Conf. on Nano/Micro Engineered and Molecular Systems (NEMS), Xi'an, China, 2015, pp. 511514.
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