access icon free Estimation of switching characteristics in quantum-dot cellular automata using probability model

© The Institution of Engineering and Technology
Received 25/09/2013, Accepted 10/12/2013, Published 16/01/2014

Quantum-dot cellular automata (QCA) is a novel computational paradigm which utilises the quantum mechanism to encode and process bit information. The switching characteristics of the QCA majority gate are evaluated by using the proposed probability model. All kinds of probabilities are achieved by solving the time-independent Schrodinger equation. The simulation results reveal that the majority gate switches at a higher correct probability when the cell distance and the size decrease. Cell miniaturisation would raise a significant implication in how to realise reliable QCA fabrication. In addition, the results also illuminate that majority output has different probabilities when the inputs change. Therefore, to analyse the QCA circuit reliability by using the probability model, all the input combinations must be considered.

Inspec keywords: Schrodinger equation; circuit reliability; cellular automata; probability; switching; quantum dots

Other keywords: switching characteristics; circuit reliability; probability model; quantum-dot cellular automata; time-independent Schrodinger equation; cell miniaturisation

Subjects: Automata theory; Reliability; Probability and statistics

References

    1. 1)
    2. 2)
    3. 3)
    4. 4)
    5. 5)
    6. 6)
    7. 7)
    8. 8)
    9. 9)
    10. 10)
    11. 11)
      • 6. ITRS: ‘International technology roadmap for semiconductors 2006 update edition’. Technical report, ITRS, 2011.
    12. 12)
    13. 13)
      • 21. Timler, J., Lent, C.S.: ‘Power gain and dissipation in quantum-dot cellular automata’, J. Appl. Phys., 2002, 91, (2), pp. 823–831 (doi: 10.1063/1.1421217).
    14. 14)
      • 4. Tougaw, P.D., Lent, C.S.: ‘Logical devices implemented using quantum cellular automata’. Appl. Phys., 1994, 75, pp. 1818–1825 (doi: 10.1063/1.356375).
    15. 15)
      • 6. ITRS: ‘International technology roadmap for semiconductors 2006 update edition’. Technical report, ITRS, 2011.
    16. 16)
      • 17. Patel, K.N., Markov, I.L., Hayes, J.P.: ‘Evaluating circuit reliability under probabilistic gate-level fault models’. Proc. Int. Workshop Logic Synthesis (IWLS'30), Laguna Beach, CA, USA, 2003, pp. 59–65.
    17. 17)
      • 20. Thara, R., Sanjukta, B.: ‘Scalable probabilistic computing models using Bayesian networks’. Circuits and Systems, 48th Midwest Symp., Covington, England, 2005, pp. 712–715.
    18. 18)
      • 19. Sanjukta, B., Sudeep, S.: ‘Probabilistic modeling of QCA circuits using Bayesian networks’, IEEE Trans. Nanotechnol., 2006, 5, (6), pp. 657–670 (doi: 10.1109/TNANO.2006.883474).
    19. 19)
      • 7. Tougaw, P., Lent, C.: ‘Dynamic behavior of quantum cellular automata’, J. Appl. Phys., 1996, 80, (8), pp. 4722–4736 (doi: 10.1063/1.363455).
    20. 20)
      • 3. Lent, C.S., Tougaw, P.D., Porod, W., et al: ‘Quantum cellular automata’, Nanotechnology, 1993, 4, (1), pp. 49–57 (doi: 10.1088/0957-4484/4/1/004).
    21. 21)
      • 10. Jie, H., Taylor, E., Gao, J., Fortes, J.: ‘Faults, error bounds and reliability of nanoelectronic circuits’. Proc. 16th Int. Conf. on Application-Specific Systems, Architecture and Processors, Samos, Greece, 2005, pp. 247–253.
    22. 22)
      • 8. Lent, C.S., Tougaw, P.D.: ‘A device architecture for computing with quantum dots’, Proc. IEEE, 1997, 85, (4), pp. 541–557 (doi: 10.1109/5.573740).
    23. 23)
      • 18. Krishnaswamy, S., Markov, I.L., Hayes, J.P.: ‘Accurate reliability evaluation and enhancement via probabilistic transfer matrices’. Proc. of Conf. on Design Automation and Test in Europe, Munich, Germany, 2005, pp. 282–287.
    24. 24)
      • 16. Goldstein, S.C., Budiu, M.: ‘Nanofabrics: spatial computing using molecular electronics’. Proc. Annual Int. Symp. Computer Architecture (ISCA), Goteborg, Sweden, 2001, pp. 178–189.
    25. 25)
      • 15. Heath, J., Kuekes, P., Snider, G., Williams, R.: ‘A defect tolerant computer architecture: opportunities for nanotechnology’, Science, 1998, 80, pp. 1716–1721 (doi: 10.1126/science.280.5370.1716).
    26. 26)
      • 14. Nikolic, K., Sadek, A., Forshaw, M.: ‘Architectures for reliable computing with unreliable nanodevices’. Proc. IEEE Nano'01, Maui, HI, USA, 2001, pp. 254–259.
    27. 27)
      • 11. Timothy, J., Dysart, P.M., et al: ‘Reliability impact of n-modular redundancy in QCA’, IEEE Trans. Nanotechnol., 2011, 10, (5), pp. 1105–1122.
    28. 28)
      • 5. Thapliyal, H., Ranganathan, N., Kotiyal, S.: ‘Design of testable reversible sequential circuits’. IEEE Trans. Very Large Scale Integr. (VLSI) Syst., 2012, 21, pp. 1201–1209 doi:10.1109/TVLSI.2012.2209688.
    29. 29)
      • 12. Bhaduri, D., Shukla, S., Graham, P., et al: ‘Comparing reliability-redundancy tradeoffs for two Von Neumann multiplexing architectures’, IEEE Trans. Nanotechnol., 2007, 6, (3), pp. 265–279 (doi: 10.1109/TNANO.2007.891504).
    30. 30)
      • 1. Peercy, P.S.: ‘The drive to miniaturization’, Nature, 2000, 406, pp. 1023–1026 (doi: 10.1038/35023223).
    31. 31)
      • 13. Beckett, P., Jennings, A.: ‘Towards nanocomputer architecture’. Proc. 7th Asia-Pacific Conf. Computer Systems Architecture, Melbourne, Australia, 2002, pp. 141–150.
    32. 32)
      • 9. Pudi, V., Sridharan, K.: ‘Low complexity design of ripple carry and Brent-Kung adders in QCA’, IEEE Trans. Nanotechnol., 2012, 11, (1), pp. 105–119 (doi: 10.1109/TNANO.2011.2158006).
    33. 33)
      • 2. Meindl, J.D.: ‘Beyond Moore's Law: the interconnect era’. Comp. Sci. Eng., 2003, January/February, 5, pp. 20–24 (doi: 10.1109/MCISE.2003.1166548).
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