access icon openaccess FPGA-based fault injection design for 16K-point FFT processor

There are a number of satellites working in the harsh space environment. The charged particles in space may strike the electron devices causing the undesired influences, such as soft errors in memory devices or permanent damage in hardware circuits. Aiming at reliability evaluation of very-large-scale integration circuits implemented in SRAM-based field programmable gate arrays, a fault injection platform is constructed based on the soft error mitigation controller in this study. The authors adopt a 16K-point fast Fourier transformation processor as the design under test (DUT) and inject errors into different positions. The effectiveness of this platform is varied by comparing the results of DUT with Golden data. Compared with the traditional reliability testing techniques, the fault injection method proposed in this study has the advantages of low cost, short test period and low resource consumption. Hence, the proposed fault injection design is suitable for circuits consuming huge resources and large number of repeating tests.

Inspec keywords: integrated circuit design; VLSI; space vehicle electronics; radiation hardening (electronics); integrated circuit reliability; SRAM chips; fast Fourier transforms; integrated circuit testing; field programmable gate arrays; microprocessor chips

Other keywords: 16K-point fast Fourier transformation processor; very-large-scale integration circuits; memory devices; reliability evaluation; soft error mitigation controller; FPGA-based fault injection design; design under test; transformation processor; field programmable gate arrays; fault injection method; satellites; DUT; electron devices; resource consumption; permanent damage; hardware circuits; reliability testing techniques; Golden data; 16K-point FFT processor; SRAM

Subjects: Integral transforms; Logic circuits; Microprocessor chips; Semiconductor storage; Digital circuit design, modelling and testing; Integral transforms; Memory circuits; Reliability; Space vehicle electronics; Logic and switching circuits; Microprocessors and microcomputers; Radiation effects (semiconductor technology)

References

    1. 1)
      • 1. Asadi, G.H., Tahoori, M.B.: ‘Soft error mitigation for SRAM-based FPGAs’. IEEE Symp. on VLSI Test IEEE Computer Society, 2005, pp. 207212.
    2. 2)
      • 8. Souari, A., Thibeault, C., Blaquière, Y., et al: ‘An automated fault injection for evaluation of LUTs robustness in SRAM-based FPGAs’. IEEE East-West Design & Test Symp., Kosice, Slovakia, April 2016, pp. 14.
    3. 3)
      • 5. Sari, A., Psarakis, M.: ‘A fault injection platform for the analysis of soft error effects in FPGA soft processors’. IEEE, Int. Symp. on Design and Diagnostics of Electronic Circuits & Systems, Kosice, Slovakia, April 2016, pp. 17.
    4. 4)
      • 2. Maurer, R.H., Fraeman, M.E., Martin, M.N., et al: ‘Harsh environments: space radiation environment effects and mitigation’, John Hopkings APL Tech. Dig., 2008, 28, (1), pp. 1729.
    5. 5)
      • 6. Siegle, F., Vladimirova, T., Emam, O.: ‘Mitigation of radiation effects in SRAM-based FPGAs for space applications’, ACM Comput. Surv., 2015, 47, (2), pp. 134.
    6. 6)
      • 9. Ingemarsson, C., Kallstrom, P., Qureshi, F., et al: ‘Efficient FPGA mapping of pipeline SDF FFT cores’, IEEE Trans. Very Large Scale Integr. Syst., 2017, 25, (9), pp. 24862497.
    7. 7)
      • 3. Lesea, A., Drimer, S., Fabula, J.J., et al: ‘The Rosetta experiment: atmospheric soft error rate testing in differing technology FPGAs’, IEEE Trans. Device Mater. Reliab., 2005, 5, (3), pp. 317328.
    8. 8)
      • 7. Tarrillo, J., Tonfat, J., Tambara, L., et al: ‘Multiple fault injection platform for SRAM-based FPGA based on ground-level radiation experiments’. IEEE Test Symp., Puerto Vallarta, Mexico, March 2015, pp. 16.
    9. 9)
      • 4. González-Toral, R., Reviriego, P., Maestro, J.A., et al: ‘A scheme to design concurrent error detection techniques for the fast Fourier transform implemented in SRAM-based FPGAs’, IEEE Trans. Comput., 2018, 1, (1), p. 99.
http://iet.metastore.ingenta.com/content/journals/10.1049/joe.2019.0703
Loading

Related content

content/journals/10.1049/joe.2019.0703
pub_keyword,iet_inspecKeyword,pub_concept
6
6
Loading