FPGA-based fault injection design for 16K-point FFT processor
- Author(s): Chuang-An Mao 1, 2 ; Yu Xie 1, 2 ; Xin Wei 1, 2 ; Yi-Zhuang Xie 1, 2 ; He Chen 1, 2
-
-
View affiliations
-
Affiliations:
1:
Radar Research Lab, School of Information and Electronics, Beijing Institute of Technology , Beijing 100081 , People's Republic of China ;
2: Beijing Key Laboratory of Embedded Real-time Information Processing Technology , Beijing Institute of Technology , Beijing 100081 , People's Republic of China
-
Affiliations:
1:
Radar Research Lab, School of Information and Electronics, Beijing Institute of Technology , Beijing 100081 , People's Republic of China ;
- Source:
Volume 2019, Issue 21,
November
2019,
p.
7994 – 7997
DOI: 10.1049/joe.2019.0703 , Online ISSN 2051-3305
Full text loading...
Inspec keywords: integrated circuit design; VLSI; space vehicle electronics; radiation hardening (electronics); integrated circuit reliability; SRAM chips; fast Fourier transforms; integrated circuit testing; field programmable gate arrays; microprocessor chips
Other keywords: 16K-point fast Fourier transformation processor; very-large-scale integration circuits; memory devices; reliability evaluation; soft error mitigation controller; FPGA-based fault injection design; design under test; transformation processor; field programmable gate arrays; fault injection method; satellites; DUT; electron devices; resource consumption; permanent damage; hardware circuits; reliability testing techniques; Golden data; 16K-point FFT processor; SRAM
Subjects: Integral transforms; Logic circuits; Microprocessor chips; Semiconductor storage; Digital circuit design, modelling and testing; Integral transforms; Memory circuits; Reliability; Space vehicle electronics; Logic and switching circuits; Microprocessors and microcomputers; Radiation effects (semiconductor technology)
References
-
-
1)
-
1. Asadi, G.H., Tahoori, M.B.: ‘Soft error mitigation for SRAM-based FPGAs’. IEEE Symp. on VLSI Test IEEE Computer Society, 2005, pp. 207–212.
-
-
2)
-
8. Souari, A., Thibeault, C., Blaquière, Y., et al: ‘An automated fault injection for evaluation of LUTs robustness in SRAM-based FPGAs’. IEEE East-West Design & Test Symp., Kosice, Slovakia, April 2016, pp. 1–4.
-
-
3)
-
5. Sari, A., Psarakis, M.: ‘A fault injection platform for the analysis of soft error effects in FPGA soft processors’. IEEE, Int. Symp. on Design and Diagnostics of Electronic Circuits & Systems, Kosice, Slovakia, April 2016, pp. 1–7.
-
-
4)
-
2. Maurer, R.H., Fraeman, M.E., Martin, M.N., et al: ‘Harsh environments: space radiation environment effects and mitigation’, John Hopkings APL Tech. Dig., 2008, 28, (1), pp. 17–29.
-
-
5)
-
6. Siegle, F., Vladimirova, T., Emam, O.: ‘Mitigation of radiation effects in SRAM-based FPGAs for space applications’, ACM Comput. Surv., 2015, 47, (2), pp. 1–34.
-
-
6)
-
9. Ingemarsson, C., Kallstrom, P., Qureshi, F., et al: ‘Efficient FPGA mapping of pipeline SDF FFT cores’, IEEE Trans. Very Large Scale Integr. Syst., 2017, 25, (9), pp. 2486–2497.
-
-
7)
-
3. Lesea, A., Drimer, S., Fabula, J.J., et al: ‘The Rosetta experiment: atmospheric soft error rate testing in differing technology FPGAs’, IEEE Trans. Device Mater. Reliab., 2005, 5, (3), pp. 317–328.
-
-
8)
-
7. Tarrillo, J., Tonfat, J., Tambara, L., et al: ‘Multiple fault injection platform for SRAM-based FPGA based on ground-level radiation experiments’. IEEE Test Symp., Puerto Vallarta, Mexico, March 2015, pp. 1–6.
-
-
9)
-
4. González-Toral, R., Reviriego, P., Maestro, J.A., et al: ‘A scheme to design concurrent error detection techniques for the fast Fourier transform implemented in SRAM-based FPGAs’, IEEE Trans. Comput., 2018, 1, (1), p. 99.
-
-
1)
Related content
