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access icon openaccess FPGA-based fault injection design for 16K-point FFT processor

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References

    1. 1)
      • 1. Asadi, G.H., Tahoori, M.B.: ‘Soft error mitigation for SRAM-based FPGAs’. IEEE Symp. on VLSI Test IEEE Computer Society, 2005, pp. 207212.
    2. 2)
      • 8. Souari, A., Thibeault, C., Blaquière, Y., et al: ‘An automated fault injection for evaluation of LUTs robustness in SRAM-based FPGAs’. IEEE East-West Design & Test Symp., Kosice, Slovakia, April 2016, pp. 14.
    3. 3)
      • 5. Sari, A., Psarakis, M.: ‘A fault injection platform for the analysis of soft error effects in FPGA soft processors’. IEEE, Int. Symp. on Design and Diagnostics of Electronic Circuits & Systems, Kosice, Slovakia, April 2016, pp. 17.
    4. 4)
      • 2. Maurer, R.H., Fraeman, M.E., Martin, M.N., et al: ‘Harsh environments: space radiation environment effects and mitigation’, John Hopkings APL Tech. Dig., 2008, 28, (1), pp. 1729.
    5. 5)
      • 6. Siegle, F., Vladimirova, T., Emam, O.: ‘Mitigation of radiation effects in SRAM-based FPGAs for space applications’, ACM Comput. Surv., 2015, 47, (2), pp. 134.
    6. 6)
      • 9. Ingemarsson, C., Kallstrom, P., Qureshi, F., et al: ‘Efficient FPGA mapping of pipeline SDF FFT cores’, IEEE Trans. Very Large Scale Integr. Syst., 2017, 25, (9), pp. 24862497.
    7. 7)
      • 3. Lesea, A., Drimer, S., Fabula, J.J., et al: ‘The Rosetta experiment: atmospheric soft error rate testing in differing technology FPGAs’, IEEE Trans. Device Mater. Reliab., 2005, 5, (3), pp. 317328.
    8. 8)
      • 7. Tarrillo, J., Tonfat, J., Tambara, L., et al: ‘Multiple fault injection platform for SRAM-based FPGA based on ground-level radiation experiments’. IEEE Test Symp., Puerto Vallarta, Mexico, March 2015, pp. 16.
    9. 9)
      • 4. González-Toral, R., Reviriego, P., Maestro, J.A., et al: ‘A scheme to design concurrent error detection techniques for the fast Fourier transform implemented in SRAM-based FPGAs’, IEEE Trans. Comput., 2018, 1, (1), p. 99.
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