access icon openaccess Dynamic partial reconfiguration scheme for fault-tolerant FFT processor based on FPGA

The fast Fourier transform FFT processor is an important part of the space real-time signal processing system based on field programmable gate array (FPGA). Since occupying a large amount of logical resources and storage resources, FFT processor is more vulnerable to high-energy particles in space, resulting in single event upset (SEU). This paper presents a novel FPGA scrubbing framework base on dynamic partial reconfiguration technique for a FFT processor to mitigate SEU. The proposed scheme is compared with the blind scrubbing, the reconfiguration time is reduced by 78%. Then, the resource utilisation is 61.5% less than triple modular redundancy scheme. This paper also presents a DPR controller for FFT processor, which is evaluated in terms of hardware resources and reconfiguration time. A comparison to the Xilinx PRC IP shows that multipath delay feedback FFT controller saves 38.6% resources.

Inspec keywords: radiation hardening (electronics); redundancy; fast Fourier transforms; field programmable gate arrays; fault tolerant computing; microprocessor chips

Other keywords: triple modular redundancy scheme; dynamic partial reconfiguration technique; field programmable gate array; multipath delay feedback FFT controller; reconfiguration time; fault-tolerant FFT processor; DPR controller; novel FPGA scrubbing framework; storage resources; logical resources; blind scrubbing; high-energy particles; dynamic partial reconfiguration scheme; Xilinx PRC IP; single event upset; fast Fourier transform FFT processor

Subjects: Microprocessors and microcomputers; Reliability; Integral transforms; Integral transforms; Radiation effects (semiconductor technology); Logic circuits; Digital circuit design, modelling and testing; Logic and switching circuits; Microprocessor chips

References

    1. 1)
      • 2. Asadi, G.H., Tahoori, M.B.: ‘Soft error mitigation for SRAM based FPGAs’. Proc. 23rd IEEE VLSI Test Symp., 2005, pp. 207212.
    2. 2)
      • 5. Brosser, F., Milh, E., Geijer, V., et al: ‘Assessing scrubbing techniques for Xilinx SRAM-based FPGAs in space applications’. Int. Conf. Field-Programmable Technology (FPT), China, Shanghai, 2014, pp. 296299.
    3. 3)
      • 6. Carmichael, C., Caffrey, M., Salazar, A.: ‘Correcting single-event upsets through virtex partial configuration’, Encyclopedia of Genetics Genomics Proteomics & Informatics, 2000.
    4. 4)
      • 9. Le, R.: ‘Soft error mitigation using prioritized essential bits’, XAPP538, Xilinx, San Jose, CA, 2012.
    5. 5)
      • 10. Xilinx: ‘Vivado design suite tutorial partial reconfiguration’, UG947, 2017.
    6. 6)
      • 8. Yang, C., Wei, C., Xie, Y., et al: ‘Area-efficient mixed-radix variable-length FFT processor’, IEICE Electron. Express, 2017, 14, (10).
    7. 7)
      • 7. Cooley, J.W., Tukey, J.W.: ‘An algorithm for the machine calculation of complex Fourier series’, Math. Comput., 1965, 19.
    8. 8)
      • 4. Tanoue, S., Ishida, T., Ichinomiya, Y., et al: ‘A novel states recovery technique for the TMR softcore processor’. IEEE Int. Conf. on Field Programmable Logic and Applications, 2009, pp. 543546.
    9. 9)
      • 1. Felix, S., Tanya, V., Jrgen, I., et al: ‘Mitigation of radiation effects in SRAM-based FPGAs for space applications’, ACM Comput. Surv., 2015, 47, (2), pp. 2734.
    10. 10)
      • 3. Ahmed, A.: ‘New FPGA blind scrubbing technique’. IEEE Aerospace Conf., 2016, pp. 19.
http://iet.metastore.ingenta.com/content/journals/10.1049/joe.2019.0353
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