access icon openaccess Fault-tolerant method for anti-SEU of embedded system based on dual-core processor

The development of space applications based on commercial system on chip (SOC) FPGA devices has become an important direction for the development of aerospace technology, but single event upsets (SEUs) in space is a difficult problem for commercial SOC FPGAs for space applications. This article presents an anti-anti method for ARM processors in SOC FPGA. This method makes full use of the hardware resources of dual-core ARM in SoC FPGA and improves the system's anti-SEU capability through dual-core mutual-check and recovery mechanisms. At the same time, the data stream and control flow fault tolerant are used to improve the anti-SEU capability within the processor. Error detection and correction (EDAC) and triple modular redundancy (TMR) are used to improve anti-SEU capability of the data flow. A two-level watchdog and ARM exception handling are used to achieve the anti-SEU capability of the control flow. Experimental results show that the two-level fault-tolerance mechanism proposed here improves the system's anti-SEU capability without adding additional hardware resources. This method is currently carrying out satellite-borne ground application verification.

Inspec keywords: field programmable gate arrays; system-on-chip; microprocessor chips; redundancy; embedded systems; fault tolerant computing; radiation hardening (electronics); error detection

Other keywords: control flow; two-level watchdog; dual-core processor; antiSEU capability; two-level fault-tolerance mechanism; embedded system; antianti method; triple modular redundancy; SoC FPGA; dual-core mutual-check; fault-tolerant method; dual-core ARM; ARM processors

Subjects: Logic circuits; Microprocessor chips; Reliability; System-on-chip; System-on-chip; Radiation effects (semiconductor technology); Logic and switching circuits; Microprocessors and microcomputers

References

    1. 1)
      • 2. Liu, G.P., Zhang, S.: ‘A survey on formation control of small satellites’, Proc. IEEE, 2018, 106, (3), pp. 440457.
    2. 2)
      • 12. Shen, Z., Feng, C., Gao, S., et al: ‘Study on FPGA SEU mitigation for the readout electronics of DAMPE BGO calorimeter in space’, IEEE Trans. Nucl. Sci., 2015, 62, (3), pp. 10101015.
    3. 3)
      • 3. Chielle, E., Rosa, F., Rodrigues, G. S., et al: ‘Reliability on ARM processors aagainst soft errors through SIHFT techniques’, IEEE Trans. Nucl. Sci., 2016, 63, (4), pp. 22082216.
    4. 4)
      • 9. Abdelhai, L., Zohir, I., Samir, S., et al: ‘Contribution to the implementation of image mosaicing algorithm on FPGA using NIOS II softcore’. 2015 3rd International Conference on Control, Engineering & Information Technology (CEIT), Tlemcen, Algeria, 2015, pp. 15.
    5. 5)
      • 8. Colodro-Conde, C., Toledo-Moreo, R.: ‘Design and analysis of efficient synthesis algorithms for EDAC functions in FPGAs’, IEEE Trans. Aerosp. Electron. Syst., 2015, 51, (4), pp. 33323347.
    6. 6)
      • 10. Wilson, C., Sabogal, S., George, A., et al: ‘Hybrid, adaptive, and reconfigurable fault tolerance’. 2017 IEEE Aerospace Conf., Big Sky, MT, USA, 2017, pp. 111.
    7. 7)
      • 4. Ma, N., Wang, S., Ali, S.M., et al: ‘High efficiency On-board hyperspectral image classification with zynq SoC’. 2016 7th Int. Conf. on Mechatronics and Manufacturing (ICMM 2016), New York, NY, USA, 2016, pp. 16.
    8. 8)
      • 7. Villata, I., Bidarte, U., Kretzschmar, U., et al: ‘Fast and accurate SEU-tolerance characterization method for zynq SoCs’. 24th Int. Conf. on Field Programmable Logic and Applications (FPL), Munich, Germany, 2014, pp. 14.
    9. 9)
      • 1. Leite, F.G.H., Aguiar, V.A.P., Added, N., et al: ‘Fast and Low-cost soft error testing of a COTS microcontroller with alpha particle source’. 2017 IEEE Radiation Effects Data Workshop (REDW), New Orleans, LA, USA, 2017, pp. 1821.
    10. 10)
      • 6. Benfica, J., Green, B., Porcher, B.C., et al: ‘Analysis of FPGA SEU sensitivity to combined effects of conducted EMI and TID’. IEEE Asia-Pacific Int. Symp. on Electromagnetic Compatibility, Shenzhen, China, 2016, pp. 887889.
    11. 11)
      • 5. Fayyaz, M., Vladimirova, T.: ‘Fault-tolerant distributed approach to satellite on-board computer design’. IEEE Aerospace Conf., Big Sky, MT, USA, 2014, pp. 112.
    12. 12)
      • 11. Gasiot, G., Giot, D., Roche, P.: ‘Alpha-induced multiple cell upsets in standard and radiation hardened SRAMs manufactured in a 65 nm CMOS technology’, IEEE Trans. Nucl. Sci., 2006, 53, (6), pp. 34793486.
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