Fault-tolerant method for anti-SEU of embedded system based on dual-core processor
- Author(s): Xiuhai Cui 1 ; Qi Gao 2 ; Ruichao Wang 1 ; Li Liu 2 ; Jun Liang 1 ; Yu Peng 1
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View affiliations
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Affiliations:
1:
Harbin Institute of Technology , Harbin , People's Republic of China ;
2: China Aerospace Science and Industry Corporation , Beijing , People's Republic of China
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Affiliations:
1:
Harbin Institute of Technology , Harbin , People's Republic of China ;
- Source:
The Journal of Engineering,
0pp.
DOI: 10.1049/joe.2018.9099 , Online ISSN 2051-3305 Available online: 24 October 2019
This is an open access article published by the IET under the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0/)
Received 12/10/2018,
Accepted 09/01/2019,
Published 25/03/2019

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Other keywords: control flow; two-level watchdog; dual-core processor; antiSEU capability; two-level fault-tolerance mechanism; embedded system; antianti method; triple modular redundancy; SoC FPGA; dual-core mutual-check; fault-tolerant method; dual-core ARM; ARM processors
Subjects: Logic circuits; Microprocessor chips; Reliability; System-on-chip; System-on-chip; Radiation effects (semiconductor technology); Logic and switching circuits; Microprocessors and microcomputers
References
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