http://iet.metastore.ingenta.com
1887

access icon openaccess Interface algorithm development for PHIL simulations of MMC-HVDC devices via real-time impedance matching

  • HTML
    67.9052734375Kb
  • XML
    62.650390625Kb
  • PDF
    3.5628137588500977MB
Loading full text...

Full text loading...

/deliver/fulltext/10.1049/joe.2018.8691/JOE.2018.8691.html;jsessionid=1cwbpky5fuphk.x-iet-live-01?itemId=%2fcontent%2fjournals%2f10.1049%2fjoe.2018.8691&mimeType=html&fmt=ahah

References

    1. 1)
      • 1. Kotsampopoulos, P., Lehfuss, F., Lauss, G.: ‘The limitations of digital simulation and the advantages of PHIL testing in studying distributed generation provision of ancillary services’, IEEE Trans. Ind. Electr., 2015, 62, (9), pp. 55025515.
    2. 2)
      • 2. Saad, H., Peralta, J., Dennetière, S., et al: ‘Dynamic averaged and simplified models for MMC-based HVDC transmission systems’, IEEE Trans. Power Deliv., 2013, 28, (3), pp. 17231730.
    3. 3)
      • 3. Xu, J., Gole, A.M., Zhao, C.: ‘The use of averaged-value model of modular multilevel converter in DC grid’, IEEE Trans. Power Deliv., 2015, 30, (2), pp. 519528.
    4. 4)
      • 4. Matar, M., Paradis, D., Iravani, R.: ‘Real-time simulation of modular multilevel converters for controller hardware-in-the-loop testing’, IET Power Electr., 2016, 9, (1), pp. 4250.
    5. 5)
      • 5. Mahdi, D.: ‘Stability analysis and implementation of Power-Hardware-in-the-Loop for power system testing’. PhD thesis, Queensland University of Technology, 2015.
    6. 6)
      • 6. Ren, W., Sloderbeck, M.: ‘Interfacing issues in real-time digital simulators’, IEEE Trans. Power Deliv., 2011, 26, (2), pp. 12211230.
    7. 7)
      • 7. Lin, C.Q., Jiang, S.Q., Chen, H.H.: ‘An improved interface algorithm of power hardware-in-the-loop simulation for MMC-HVDC’, J. Northeast Electr. Power Univ., 2016, 36, (2), pp. 16.
    8. 8)
      • 8. Ren, W., Steurer, M., Baldwin, T.L.: ‘Improve the stability and the accuracy of power hardware-in-the-loop simulation by selecting appropriate interface algorithms’, IEEE Trans. Ind. Appl., 2008, 44, (4), pp. 12861294.
    9. 9)
      • 9. Xin, Y.C., Jiang, S.Q., Li, G.Q., et al: ‘Review on interface algorithms of power hardware-in-the-loop simulation for power systems’, Autom. Electr. Power Syst., 2016, 40, (15), pp. 159167.
    10. 10)
      • 10. Paran, S., Edrington, C.S., Vural, B.: ‘Investigation of HIL interfaces in nonlinear load studies’. NAPS Conf., Champaign, IL, September 2012, pp. 16.
    11. 11)
      • 11. Paran, S., Edrington, C.S.: ‘Improved power hardware in the loop interface methods via impedance matching’. IEEE ESTS Conf., Arlington, VA, April 2013, pp. 342346.
    12. 12)
      • 12. Paran, S., Fleming, F., Li, D., et al: ‘Utilization of adaptive PHIL interfaces for harmonic load cases’. IECON Annual Conf. of IEEE Industrial Electronics Society, Dallas, TX, November 2014, pp. 38033808.
    13. 13)
      • 13. Siegers, J., Santi, E.: ‘Improved power hardware-in-the-loop interface algorithm using wideband system identification’. IEEE Applied Power Electronics Conf. (APEC), Fort Worth, TX, March 2014, pp. 11981204.
    14. 14)
      • 14. Gnanarathna, U.N., Gole, A.M., Jayasinghe, R.P.: ‘Efficient modeling of modular multilevel HVDC converters (MMC) on electromagnetic transient simulation programs’, IEEE Trans. Power Deliv., 2011, 26, (1), pp. 316324.
    15. 15)
      • 15. Saad, H., Dennetière, S., Mahseredjian, J., et al: ‘Modular multilevel converter models for electromagnetic transients’, IEEE Trans. Power Deliv., 2014, 29, (3), pp. 14811489.
    16. 16)
      • 16. Xu, J., Zhao, C., Gole, A.M.: ‘Research on the Thévenin's equivalent based integral modeling method of the modular multilevel converter’, Proc. CSEE, 2015, 35, (8), pp. 19191929.
    17. 17)
      • 17. Li, G.Q., Jiang, S.Q., Xin, Y.C., et al: ‘An improved DIM interface algorithm for the MMC-HVDC power hardware in-the-loop simulation system’, Int. J. Electr. Power Energy Syst., 2018, 99, pp. 6978.
    18. 18)
      • 18. Guillo-Sansano, E., Roscoe, A.J.: ‘A new control method for the power interface in power hard-in-the-loop simulation to compensate for the time delay’. Int. Universities Power Engineering Conf. (UPEC), Cluj-Napoca, September 2014, pp. 15.
http://iet.metastore.ingenta.com/content/journals/10.1049/joe.2018.8691
Loading

Related content

content/journals/10.1049/joe.2018.8691
pub_keyword,iet_inspecKeyword,pub_concept
6
6
Loading
This is a required field
Please enter a valid email address